Car Stereo System - Car Radio Digital Signal Processor User Manual

www.ti.com
GMTCLK
(Output)
2 3
1
4
4
MRCLK (Input)
1
2
MRXD7−MRXD4(GMII only),
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Table 7-77. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII
Operation (see Figure 7-61 )
-720
-850
A-1000/-1000
NO. UNIT
-1200
1000 Mbps
MIN MAX
1 t
c(GMTCLK)
Cycle time, GMTCLK 8 ns
2 t
w(GMTCLKH)
Pulse duration, GMTCLK high 2.8 ns
3 t
w(GMTCLKL)
Pulse duration, GMTCLK low 2.8 ns
4 t
t(GMTCLK)
Transition time, GMTCLK 1 ns
Figure 7-61. GMTCLK Timing (EMAC – Transmit) [GMII Operation]
Table 7-78. Timing Requirements for EMAC MII and GMII Receive 10/100/1000 Mbit/s
(1)
(see Figure 7-62 )
-720
-850
A-1000/-1000
NO. UNIT
-1200
1000 Mbps 100/10 Mbps
MIN MAX MIN MAX
Setup time, receive selected signals valid before
1 t
su(MRXD-MRCLKH)
2 8 ns
MRCLK high
Hold time, receive selected signals valid after
2 t
h(MRCLKH-MRXD)
0 8 ns
MRCLK high
(1) For MII, Receive selected signals include: MRXD[3:0], MRXDV, and MRXER. For GMII, Receive selected signals include: MRXD[7:0],
MRXDV, and MRXER.
Figure 7-62. EMAC Receive Interface Timing [MII and GMII Operation]
Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 209