Car Stereo System - Car Radio Digital Signal Processor User Manual

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SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Interface Mode Clocking
The on-chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode.
When the EMAC is enabled with these modes, the input clock to the PLL2 Controller (CLKIN2) must have
a 25-MHz frequency. For more information, see Section 7.8 , PLL2 and PLL2 Controller.
The EMAC uses SYSCLK1 of the PLL2 Controller to generate the necessary clocks for the GMII and
RGMII modes. When these modes are used, the frequency of CLKIN2 must be 25 MHz. Also, divider D1
should be programmed to ÷ 2 mode [default] when using the GMII mode and to ÷ 5 mode when using the
RGMII mode. Divider D1 is software programmable and, if necessary, must be programmed after device
reset to ÷ 5 when the RGMII mode of the EMAC is used.
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