Incor. User's Guide Buck Converter SLVU013

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June 1999 Mixed-Signal Linear Products

User’s Guide

SLVU013

Summary of content (64 pages)

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User’s Guide June 1999 Mixed-Signal Linear Products SLVU013
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
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Information About Cautions and Warnings Preface Read This First About This Manual This user’s guide describes techniques for designing synchronous buck converters using TI’s SLVP1111–114 evaluation modules (EVM) and TPS56xx ripple regulator controllers. How to Use This Manual This document contains the following chapters: Chapter 1 Introduction Chapter 2 Design Procedure Chapter 3 Test Results Information About Cautions and Warnings This book may contain cautions and warnings.
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Trademarks Related Documentation From Texas Instruments Synchronous Buck Converter Design Using TPS56xx Controllers in SLVP10x EVMs User’s Guide (literature number SLVU007). TPS56xx data sheet (literature number SLVS177A) Designer’s Notebook The TPS56xx Family of Power Supply Controllers (literature number SLVT140A) Designing Fast Response Synchronous Buck Regulators Using the TPS5210 (literaure number SLVA044).
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Running Title—Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Synchronous Buck Regulator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Hysteretic Control Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Design Strategy . . . . . . . . . . . . . . . .
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Running Title—Attribute Reference Figures 1–1 1–2 1–3 1–4 1–5 1–6 1–7 2–1 2–2 2–3 2–4 2–5 2–6 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 3–14 3–15 3–16 3–17 3–18 3–19 3–20 3–21 3–22 3–23 3–24 3–25 3–26 vi Simplified Synchronous Buck Converter Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Simplified Hysteretic Controlled Output Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 SLVP111–114 EVM Converter Schematic Diagram . . . . . . . . .
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Running Title—Attribute Reference 3–27 3–28 3–29 3–30 3–31 3–32 3–33 3–34 3–35 3–36 3–37 SLVP113 Measured Start-Up (VIN) Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLVP113 Measured Load Transient Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLVP114 Measured Load Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLVP114 Measured Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 Introduction The SLVP111/112/113/114 evaluation modules (EVMs) have been designed and tested using the TPS56xx hysteretic controllers. These boards are synchronous dc-dc buck converters with fixed output voltages of 3.3 V, 2.5 V, 1.8 V and 1.5 V respectively. They use only surface mount components and are design examples of how to use TI’s TPS56xx controllers in high density, low loss applications with tight static and dynamic output voltage requirements.
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Synchronous Buck Regulator Operation 1.1 Synchronous Buck Regulator Operation The synchronous buck converter is a variation of the traditional buck converter. The main switching device is usually a power MOSFET and is driven in the same manner as in a traditional buck converter. The freewheeling rectifier, usually a Schottky device, is replaced by a power MOSFET and is driven in a complementary or synchronous fashion relative to the main switching device; when one MOSFET is on, the other is off.
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Hysteretic Control Operation 1.2 Hysteretic Control Operation Hysteretic control, also called bang-bang control or ripple regulator control, maintains the output voltage within the hysteresis band centered about the internal reference voltage. Figure 1–2 shows a simplified example of a hysteretic controlled output voltage using the TPS5625 with a reference voltage of 2.500 V and a hysteresis band of 50 mV.
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Design Strategy 1.3 Design Strategy The SLVP111–114 evaluation modules (EVMs) are optimized for 5-V main input voltage and 6-A output current. The EVMs need an additional low current 12-V (30 mA max) input voltage for the controller. TI’s application report, Providing a DSP Power Solution from 5 V or 3.3 V Only Systems, TI literature number SPRA525 describes how one can implement a simple boost circuit for 5-V only input voltage applications.
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Design Specification Summary 1.4 Design Specification Summary This section summarizes the design requirements of the EVM converters. Although every attempt was made to accurately describe the performance of the EVM converters and the TPS56xx controllers, in case of conflicts, the TPS56xx data sheet takes precedence over this document. The TPS56xx family of controllers provides the necessary regulation functions.
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Design Specification Summary Table 1–2. EVM Converter Operating Specifications (Continued) Specification Min Typ Output ripple|| SLVP111 (3.3 V) SLVP112 (2.5 V) SLVP113 (1.8 V) SLVP114 (1.5 V) 66 50 36 30 Efficiency, 6 A load SLVP111 (3.3 V) SLVP112 (2.5 V) SLVP113 (1.8 V) SLVP114 (1.5 V) 90% 86.4% 83.2% 79.8% Efficiency, 4 A load SLVP111 (3.3 V) SLVP112 (2.5 V) SLVP113 (1.8 V) SLVP114 (1.5 V) 91.6% 88.6% 85.1% 81.
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J1–7 12 V RETURN J1–8 PG J1–3 J1–1 INHIBIT RETURN J1–10 J1–9 J1–6 C19 0.01 µ F C17 0.1 µ F R1 1 kΩ R2 10 kΩ R10 20 kΩ 1% R10 100 Ω 1% C20 1000 pF R11 20 kΩ 1% NOTE: Last two digits of U1 indicates output voltage option TPS5633 = 3.3 V (SLVP111) TPS5625 = 2.5 V (SLVP112) TPS5618 = 1.8 V (SLVP113) TPS5618 = 1.5 V (SLVP114) R13 750 Ω 11 kΩ R9 R7 1 kΩ 33 µ F 10 V C1 + U1 TPS5633 (See Note) J1–5 C6 0.1 µ F C5 C7 C21 0.1 µ F 1µF C16 C8 R3 10 Ω R4 L1 Q1 Si4410 C18 0.
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Bill of Materials 1.6 Bill of Materials Table 1–3 lists materials required for the SLVP111–114 EVMs. Table 1–3. SLVP111–114 EVMs Bill of Materials Ref Des Part Number Description MFG C1 10TPA33M Capacitor, POSCAP, 33 µF, 10 V, 20% Sanyo C2 6TPB150M Capacitor, POSCAP, 150 µF, 6.3 V, 20% Sanyo C3 6TPB150M Capacitor, POSCAP, 150 µF, 6.3 V, 20% Sanyo C4 6TPB150M Capacitor, POSCAP, 150 µF, 6.3 V, 20% Sanyo C5 GRM39X7R104K016A Capacitor, Ceramic, 0.
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Bill of Materials Table 1–3. SLVP111–114 EVMs Bill of Materials (Continued) Ref Des Part Number Description MFG R7 Std Resistor, Chip, 1 kΩ, 1/16W, 5% R8 Std Resistor, Chip, 100 Ω, 1/16W, 1% R9 Std Resistor, Chip, 11 kΩ, 1/16W, 5% R10 Std Resistor, Chip, 100 Ω, 1/16W, 1% R11 Std Resistor, Chip, 20 kΩ, 1/16W, 1% R12 Std Resistor, Chip, 4.
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Board Layout 1.7 Board Layout Figures 1–4 through 1–7 show the board layouts for the SLVP111–114 evaluation modules. Figure 1–4. Top Assembly Top Assembly Figure 1–5. Bottom Assembly (Top View) Bottom Assembly (Top View) Figure 1–6.
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Board Layout Figure 1–7.
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1-12
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Chapter 2 Design Procedure The SLVP111–114 are dc-dc synchronous buck converter evaluation modules (EVMs) that provide a regulated output voltage at up to 6 A with a power input voltage range of 4.5 V to 6 V. A low power 12-V, 20-mA source is also required to power the TPS56xx controller. The controller operates at a nominal frequency of 135 kHz for 5 V input and 3.3 V output. To provide the highest level of performance, the EVM converters use hysteretic, or ripple, control.
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TPS56xx Functions 2.1 TPS56xx Functions The functional block diagram of the TPS56xx family of controllers is given in Figure 2–1. The controller has the following main features: ±1% reference over 0°C to125°C junction temperature range. Synchronous-buck gate drivers with adaptive deadtime control High-side MOSFET driver voltage rating of 30 V MOSFET driver peak current rating of 2 A Hysteretic comparator: 250-ns propagation delay to gate driver outputs, 2.
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TPS56xx Functions Figure 2–1. TPS56xx Functional Block Diagram 15 VCC 7 ANAGND 28 20 PWRGD LOSENSE 19 21 IOUTLO HISENSE VCC 2V + _ 22 INHIBIT UVLO 10 V 3 OCP _ 1 IOUT Shutdown S VCC 2X Q Fault Deglitch + Rising Edge Delay R HIGHDR 100mV HIGHIN Deglitch VPGD 0.93 VREF VOVP 1.
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TPS56xx Functions 2.1.2 Inhibit The inhibit circuit is a comparator with a 2.1-V start voltage and a 100-mV hysteresis. When inhibit is low, the output drivers are low and the slowstart capacitor is discharged. When inhibit is above the start threshold, the short across the slowstart capacitor is released and normal operation begins.
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TPS56xx Functions R VREFB + 3.3 V + 20 kW 165 mA This value is used to determine the values of R10 and R14 that set the hysteresis level.
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TPS56xx Functions Note that Vdel is independent of the output voltage. To calculate Vdel for this example design, use the component measurements given in Section 2.2.4.2. They are repeated here for convenience: L = 1.5 µH ESR = 10 mΩ Tdel = 400 ns Now calculate Vdel: V del + 5 1.5 10 –6 400 10 –9 10 10 –3 + 13.3 mV Since Vdel does not depend on the output voltage setting, Vdel is a larger portion of the total output voltage ripple for lower output voltages.
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TPS56xx Functions 2.1.5 Noise Suppression Hysteretic regulators, by nature, have a fast response time to VO transients and are thus inherently noise sensitive due to the very high bandwidth of the controller. Noise suppression circuits were added to the TPS56xx to improve the noise immunity, as shown in Figure 2–2. Internal low-pass filters with a pole frequency of 5 MHz were added to the inputs of the hysteretic comparator.
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TPS56xx Functions Figure 1–3). This arrangement improves efficiency over solutions having a separate current sensing resistor. The drain of the high-side MOSFET is connected to HISENSE (pin 19). The source of the high-side MOSFET is connected to LOSENSE (pin 20). When the high-side MOSFET is on, a TPS56xx internal switch is also on and samples the source voltage of the high-side MOSFET. This sampled voltage is applied to IOUTLO (pin 21) and is held by the external 0.
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TPS56xx Functions resistor-divider network is designed so that the voltage applied to OCP is 100 mV for the desired output current limit point. If the voltage on OCP exceeds 100 mV, a fault latch is set and the output drivers are turned off. The latch remains set until VCC (pin 15) goes below the undervoltage lockout value. The following equations summarize the relationships discussed above.
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TPS56xx Functions An alternate current sensing scheme is to insert a current sense resistor in series with the drain of Q1. Higher accuracy may be obtained at the expense of lower efficiency. 2.1.7 Overvoltage Protection If VO exceeds Vref by 15%, a fault latch is set and the output gate drivers are turned off. The latch remains set until VCC (pin 15) goes below the undervoltage lockout value.
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TPS56xx Functions Figure 2–4. Gate Driver Block Diagram TPS56xx Synchronous-Buck Controller VCC 8 V Drive Regulator 12 V DRV Highside Driver C3 L1 BOOT Vin M1 45 Ω VREF M2 5Ω C4 L2 LOWDR Adaptive Deadtime Control C1 HIGHDR Level Shifter/ Predriver VO BOOTLO Lowside Driver Vphase M3 45 Ω LOWDR Predriver C2 M4 5Ω DRVGND R1 R2 C5 Figure 2–5 gives an I–V sweep of the low-side driver during sinking.
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TPS56xx Functions Driver Sink Current – 0.5 A/div Figure 2–5. I–V Characteristic Curve for Low-Side Gate Drivers Driver Output Voltage – 1 V/div The high-side gate driver is a bootstrap configuration with an internally integrated Schottky bootstrap diode. The voltage rating of the BOOT pin to DRVGND is 30 V. The gate drivers are biased from an internal 8-V drive regulator to minimize the gate drive power losses that are dissipated inside the TPS55xx.
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TPS56xx Functions LOHIB (pin 11) is an inhibit input for the low-side MOSFET driver. This input has to be logic low before the low-side MOSFET is allowed to be turned on, i.e., a logic high on LOHIB prevents the low-side MOSFET driver from turning on the low-side MOSFET. For normal synchronous operation, this pin is connected to the junction of the high and low-side MOSFETs.
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External Component Selection 2.2 External Component Selection This section shows the procedure used in designing and selecting the power stage components to meet the performance parameters shown in Table 1–2 for the example circuit shown in Figure 1–3. 2.2.1 Duty Cycle Estimate An estimate of the duty cycle is used frequently in the following sections. The duty cycle, D, is the ratio of the high-side power-switch conduction time to the period of one switching cycle.
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External Component Selection performance in response to fast load transients encountered when supplying power to current- and next-generation microprocessors. A secondary consideration is the switching frequency resulting from the output filter component values. This section discusses important considerations when selecting/designing the output filter elements.
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External Component Selection for the particular application. In addition, the capacitor(s) must have an ample ripple current rating to handle the applied ripple current. This ripple current is dependent on the ripple current in the output inductance that is calculated in the next section. The RMS current in the output capacitance is calculated as follows for 3.3 V output: I CRMS + I L Ǹ3 + I L 6 0.289 + 7.3 A 0.289 + 2.1 A RMS Where ∆IL is the peak-to-peak ripple current in the output inductor.
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External Component Selection VL + L I TRAN VL åLv t I TRAN t Where: VL= the voltage applied across the output inductor, ITRAN = the magnitude of the load step, and ∆t = the desired response time. For a load step from light load to heavy load, the voltage applied across the inductor can be assumed to be VI – VO. This also assumes that the duty cycle is 100% as the output voltage is corrected.
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External Component Selection Figure 2–6.
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External Component Selection Peak to peak value of the inductor current ∆I is given by the following equation: I + V I – Io ǒRDS(on) ) RLǓ–VO L D Ts (1) Where: VI =the input voltage VO = the output voltage Ts = the switching period D+ V O ) Io ǒRDS(on) ) RLǓ VI is the duty cycle which is defined as : t D + ON and t ON is the on time of the high-side MOSFET. Ts Referring to Figure 2–6 (e), the output voltage ripple, Vp-p , is higher than the hysteresis band, Hyst, because of the delays, tdel .
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External Component Selection of power losses and additional voltage drops through non-ideal components. Equation (4) should be sufficiently accurate for the first frequency estimate at the beginning of a design. 2.2.5 Power MOSFET Selection The TPS56xx is designed to drive N-channel power MOSFETs in a synchronous rectifier configuration. The MOSFET chosen for this design is the Siliconix Si4410DY. This device is chosen for its low rDS(on) of 13.5 mΩ and drain-to-source breakdown voltage rating of 30 V.
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Chapter 3 Test Results This chapter shows the test setups used, and the test results obtained, in designing the SLVP111–114 EVMS. Topic Page 3.1 Test Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 3.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 3.2 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Test Summary 3.1 Test Summary The detailed test results and waveforms are presented in Figures 3–2 to 3–10 for the SLVP111, Figures 3–11 to 3–19 for the SLVP112, Figures 3–20 to 3–28 for the SLVP113 and Figures 3–29 to 3–37 for the SLVP114. The following are summarized results. 3.1.1 Static Line and Load Regulation The precise reference voltage regulator implemented in the TPS56XX controller using both positive and negative remote sense pins provides excellent regulation characteristics.
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Test Summary in a linear fashion. There is no discernable overshoot in the waveforms. In this application, output voltage rise time is set to approximately 9 mS with an external capacitor. Although the EVMs have been tested with a very short Vcc rise time, (see Figures 3–26 and 3–35) it is recommended to keep the rise time of Vcc longer than 3mS as shown in Figures 3–8 and 3–17. 3.1.
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Test Summary 3.1.8 Conclusion The test results of the SLVP111/112/113/114 EVMs demonstrate the advantages of TPS56xx controllers to meet stringent supply requirements to power supplies, especially for powering DSPs and microprocessors. The power system designer has a good solution to optimize system for his particular application.
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Test Setup 3.2 Test Setup Follow these steps for initial power up of the SLVP112: 1) Connect an electronic load from Vout to PwrGND (J1-15, -16, -17, -18 to J1-11, -12, -13, -14) adjusted to draw approximately 1 A at 2.5 V. The exact current is not critical; any nominal current is sufficient. A fixed resistor can also be used in place of the electronic load. The output current drawn by the resistor is I O 2.5 V amps where R is the value of the load resistor.
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Test Setup Figure 3–1.
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Test Results 3.3 Test Results Figures 3–2 to 3–102 show test results for the SLVP111. Figure 3–2. SLVP111 Measured Load Regulation SLVP111 MEASURED LOAD REGULATION 3.305 VO – V 3.3 3.295 Vin = 5 V Vin = 5.5 V 3.29 Vin = 4.5 V 3.285 0 1 2 3 IO – A 4 5 6 Figure 3–3. SLVP111Measured Efficiency SLVP111 MEASURED EFFICIENCY 94 Vin = 5 V Vin = 4.5 V 92 Efficiency – % 90 Vin = 5.
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Test Results Figure 3–4. SLVP111Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION 2.5 Ploss – W 2 1.5 Vin = 4.5 V 1 Vin = 5 V Vin = 5.5 V 0.5 0 0 1 2 3 IO – A 4 5 6 Figure 3–5. SLVP111Measured Switching Frequency SLVP111 MEASURED SWITCHING FREQUENCY 200 Frequency – kHz 175 Vin = 5.5 V 150 Vin = 5 V 125 Vin = 4.
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Test Results Figure 3–6. SLVP111 Measured Switching Waveforms C3 Pk–Pk 50.8 mV VO 20 mV/div VDS Q2 2 V/div C3 Frequency 130.088 kHz Low Signal Amplitude C4 Max 5.20 V C4 + Duty 70.4% 2.5 µs/div Figure 3–7. SLVP111Measured Start-Up (INHIBIT) Waveforms VO 2 V/div C3 Pk–Pk 3.36 V INHIBIT 1 V/div C3 Rise 7.500 ms Low Signal Amplitude C3 + Over 2.5% 2.
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Test Results Figure 3–8. SLVP111 Measured Start-Up (VCC ) Waveforms C3 Pk–Pk 3.36 V VO 2 V/div VCC (12 V) 5 V/div C3 Rise 7.300 ms Low Signal Amplitude C3 + Over 2.5% UVLO Threshold 2.5 ms/div Figure 3–9. SLVP111Measured Start-Up (VIN ) Waveforms C3 Pk–Pk 3.52 V VO 2 V/div VIN (5 V) 1 V/div C3 Rise 8.540 ms Low Signal Amplitude C3 + Over 2.4% 2.
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Test Results Figure 3–10. SLVP111 Measured Load Transient Waveforms VO 100 mV/div C3 Pk–Pk 208 mV C2 High 6.5 V IO 5 A/div 6.5 A 2.5 µs/div Figure 3–11. SLVP112 Measured Load Regulation SLVP112 MEASURED LOAD REGULATION 2.51 Vin = 5 V Vin = 5.5 V Vin = 4.5 V VO – V 2.505 2.5 2.
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Test Results Figure 3–12. SLVP112 Measured Efficiency SLVP111 MEASURED EFFICIENCY 90 Vin = 4.5 V 88 Vin = 5 V Eficiency – % 86 Vin = 5.5 V 84 82 80 78 1 2 3 4 5 6 IO – A Figure 3–13. SLVP112 Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION 2.5 Ploss – W 2 1.5 Vin = 5.5 V Vin = 5 V 1 Vin = 4.5 V 0.
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Test Results Figure 3–14. SLVP112 Measured Switching Frequency SLVP112 MEASURED SWITCHING FREQUENCY 300 Frequency – kHz 275 250 Vin = 5.5 V Vin = 5 V 225 Vin = 4.5 V 200 175 150 0 1 2 3 IO – A 4 5 6 Figure 3–15. SLVP112 Measured Switching Waveforms C3 Pk–Pk 43.2 mV VO 20 mV/div C3 Frequency 218.800 kHz Low Signal Amplitude VDS Q2 2 V/div C4 Max 5.72 V C3 + Duty 54.2% 2.
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Test Results Figure 3–16. SLVP112 Measured Start-Up (INHIBIT) Waveforms VO 1 V/div C3 Pk–Pk 2.64 V C3 Rise 7.885 ms INHIBIT 1 V/div C3 + Over 3.2% 2.5 ms/div Figure 3–17. SLVP112 Measured Start-Up (VCC ) Waveforms C3 Pk–Pk 2.56 V VO 2 V/div C3 Rise 7.995 ms VCC (12 V) 5 V/div UVLO Threshold 2.5 ms/div 3-14 C3 + Over 3.
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Test Results Figure 3–18. SLVP112 Measured Start-Up (VIN ) Waveforms C3 Pk–Pk 2.60 V VO 1 V/div C3 Rise 7.635 ms VIN (5 V) 1 V/div C3 + Over 3.2% 2.5 ms/div Figure 3–19. SLVP112 Measured Load Transient Waveforms VO 100 mV/div C3 Pk–Pk 200 mV C2 High 7.
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Test Results Figure 3–20. SLVP113 Measured Load Regulation SLVP113 MEASURED LOAD REGULATION 1.805 Vin = 5 V Vin = 5.5 V VO – V 1.8025 Vin = 4.5 V 1.8 1.7975 1.795 0 1 2 3 IO – A 4 5 6 Figure 3–21. SLVP113 Measured Efficiency SLVP113 MEASURED EFFICIENCY 88 86 Vin = 4.5 V 84 Efficiency – % Vin = 5 V 82 Vin = 5.
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Test Results Figure 3–22. SLVP113 Measured Power Dissipation SLVP113 MEASURED POWER DISSIPATION 2.5 2 Ploss – W 1.5 Vin = 5.5 V Vin = 5 V 1 Vin = 4.5 V 0.5 0 0 1 2 3 IO – A 4 5 6 Figure 3–23. SLVP113 Measured Switching Frequency SLVP113 MEASURED SWITCHING FREQUENCY 350 325 Vin = 5.5 V Frequency – kHz 300 Vin = 5 V 275 Vin = 4.
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Test Results Figure 3–24. SLVP113 Measured Switching Waveforms C3 Pk–Pk 34.8 mV VO 20 mV/div C3 Frequency 285.52 kHz Low Signal Amplitude VDS Q2 2 V/div C5 Max 5.80 V C4 + Duty 40.4% 1 µs/div Figure 3–25. SLVP113 Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk 1.88 V VO 1 V/div INHIBIT 1 V/div C3 Rise 7.360 ms Low Signal Amplitude C3 + Over 2.3% 2.
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Test Results Figure 3–26. SLVP113 Measured Start-Up (VCC ) Waveforms C3 Pk–Pk 1.84 V VO 2 V/div VCC (12 V) 5 V/div C3 Rise 7.195 ms Low Signal Amplitude C3 + Over 2.3% 2.5 ms/div Figure 3–27. SLVP113 Measured Start-Up (VIN ) Waveforms C3 Pk–Pk 1.88 V VO 1 V/div VIN (5 V) 1 V/div C3 Rise 8.300 ms Low Signal Amplitude C3 + Over 2.2% 2.
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Test Results Figure 3–28. SLVP113 Measured Load Transient Waveforms VO 100 mV/div C3 Pk–Pk 112 mV C2 High 3.64 V IO 5 A/div 3.6 A 25 µs/div Figure 3–29. SLVP114 Measured Load Regulation SLVP114 MEASURED LOAD REGULATION 1.5 1.499 1.498 1.497 VO – V 1.496 Vin = 5 V 1.495 1.494 Vin = 5.5 V Vin = 4.5 V 1.493 1.492 1.491 1.
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Test Results Figure 3–30. SLVP114 Measured Efficiency SLVP114 MEASURED EFFICIENCY 85 Vin = 4.5 V Vin = 5 V 83 81 Efficiency – % 79 77 Vin = 5.5 V 75 73 71 69 67 65 1 2 3 4 5 6 IO – A Figure 3–31. SLVP114 Measured Power Dissipation SLVP114 MEASURED POWER DISSIPATION 2.5 2 Ploss – W Vin = 5.5 V 1.5 Vin = 5 V 1 Vin = 4.5 V 0.
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Test Results Figure 3–32. SLVP114 Measured Switching Frequency SLVP114 MEASURED SWITCHING FREQUENCY 400 375 Vin = 5.5 V Frequency – kHz 350 Vin = 5 V 325 300 Vin = 4.5 V 275 250 225 200 0 1 2 3 IO – A 4 5 6 Figure 3–33. SLVP114 Measured Switching Waveforms C3 Pk–Pk 30.8 mV VO 20 mV/div VDS Q2 2 V/div C3 Frequency 337.82 kHz Low Signal Amplitude C4 Max 7.44 V C4 + Duty 36.
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Test Results Figure 3–34. SLVP114 Measured Start-Up (INHIBIT) Waveforms C3 Pk–Pk 1.56 V VO 1 V/div INHIBIT 1 V/div C3 Rise 6.990 ms Low Signal Amplitude C3 + Over 2.8% 2.5 ms/div Figure 3–35. SLVP114 Measured Start-Up (VCC ) Waveforms C3 Pk–Pk 1.56 V VO 1 V/div VCC (12 V) 5 V/div C3 Rise 7.090 ms Low Signal Amplitude C3 + Over 2.8% 2.
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Test Results Figure 3–36. SLVP114 Measured Start-Up (VIN ) Waveforms C3 Pk–Pk 1.56 V VO 1 V/div VIN (5 V) 1 V/div C3 Rise 7.07 ms Low Signal Amplitude C3 + Over 2.7% 2.5 ms/div Figure 3–37. SLVP114 Measured Load Transient Waveforms VO 50 mV/div C3 Pk–Pk 108 mV C2 High 3.