Datasheet

www.ti.com

Loss-of-Lock Indicator

Loss of Signal

Signal Detect

Multiplexer Operation

Demultiplexer Operation

Frame Synchronization

SLK2721

SLLS532B – JUNE 2002 – REVISED MARCH 2007

The SLK2721 device has a lock detection circuit to monitor the integrity of the data input. When the clock

recovery loop is locked to the input serial data stream, the LOL signal goes high. If the recovered clock

frequency deviates from the reference clock frequency by more than 100 ppm, LOL goes low. If the data stream

clock rate deviates by more than 170 ppm, loss of lock occurs. If the data streams clock rate deviates more than

500 ppm from the local reference clock, the LOL output status might be unstable. Upon power up, the LOL goes

low until the PLL is close to phase lock with the local reference clock.

The loss-of-signal (LOS) alarm is set high when no transitions appear in the input data path for more than

2.3 µ s. The LOS signal becomes active when the above condition occurs. If the serial inputs of the device are

ac-coupled to its source, the ac-coupling capacitor needs to be big enough to maintain a signal level above the

threshold of the receiver for the 2.3- µ s no transition period. Once activated, the LOS alarm pin is latched high

until the receiver detects an A1A2 pattern. The recovered clock (RXCLK) is automatically locked to the local

reference when LOS occurs. The parallel data (RXDATAx) may still be processed even when LOS is activated.

The SLK2721 device has an input SIGDET pin to force the device into the loss-of-signal state. This pin is

generally connected to the signal detect output of the optical receiver. Depending on the optics manufacturer,

this signal can be either active high or active low. To accommodate the differences, a polarity select (PS) is

used. For an active low, SIGDET input sets the PS pin high. For an active high, SIGDET input sets the PS pin

low. When the PS signal pin and SIGDET are of opposite polarities, the loss-of-signal state is generated and the

device transmits all zeroes downstream.

The 4-bit parallel LVDS data is clocked into an input buffer by a clock derived from the synthesized clock. The

data is then clocked into a 4:1 multiplexer. The D0 bit is the most significant bit and is shifted out first in the

serial output stream.

The serial 2.5-Gbps data is clocked into a 1:4 demultiplexer by the recovered clock. The D0 bit is the first bit that

is received in time from the input serial stream. The 4-bit parallel data is then sent to the LVDS driver along with

the divided down recovered clock.

The SLK2721 device has a SONET/SDH-compatible frame detection circuit that can be enabled or disabled by

the user. Frame detection is enabled when the FRAME_EN pin is high. When enabled, it detects the A1, A2

framing pattern, which is used to locate and align the byte and frame boundaries of the incoming data stream.

When FRAME_EN is low, the frame detection circuitry is disabled and the byte boundary is frozen to the location

found when detection was previously enabled.

The frame detect circuit searches the incoming data for three consecutive A1 bytes followed immediately by one

A2 byte. The data alignment circuit then aligns the parallel output data to the byte and frame boundaries of the

incoming data stream. During the framing process the parallel data bus will not contain valid and aligned data.

Upon detecting the third A1, A2 framing patterns that are separated by 125 µ s from each other, the FSYNC

signal goes high for four RXCLK cycles, indicating frame synchronization has been achieved.

The probability that random data in a SONET/SDH data stream will mimic the framing pattern in the data

payload is extremely low. However, there is a state machine built in to prevent false reframing if a framing

pattern does show up in the data payload.

Submit Documentation Feedback