Datasheet

www.ti.com
SLK2721
SLLS532B – JUNE 2002 – REVISED MARCH 2007
TERMINAL FUNCTIONS
TERMINAL
TYPE DESCRIPTION
NAME NO.
CLOCK PINS
REFCLKP 94 LVDS/PECL Differential reference input clock. There is an on-chip 100- Ω termination resistor
REFCLKN 95 compatible input differentially placed between REFCLKP and REFCLKN. The dc bias is also provided
on-chip for the ac-coupled case.
RXCLKP 67 LVDS output Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP. The
RXCLKN 68 interface of RXDATA(0:3) and RXCLKP is source synchronous (see Figure 6 ).
TXCLKP 79 LVDS input Transmit data clock. The data on TXDATA(0:3) is latched on the rising edge of
TXCLKN 80 TXCLKP.
TXCLKSRCP 70 LVDS output Transmit clock source. A clock source generated from the SLK2721 device to the
TXCLKSRCN 71 downstream device (i.e., framer) that could be used by the downstream device to
transmit data back to the SLK2721 device. This clock is frequency-locked to the local
reference clock.
SERIAL SIDE DATA PINS
SRXDIP 14 PECL compatible Receive differential pairs; high-speed serial inputs
SRXDIN 15 input
STXDOP 9 PECL compatible Transmit differential pairs; high-speed serial outputs
STXDON 8 output
PARALLEL SIDE DATA PINS
FSYNCP 73 LVDS output Frame sync pulse. This signal indicates the frame boundaries of the incoming data
FSYNCN 74 stream. If the frame-detect circuit is enabled, FSYNC pulses for four RXCLKP and
RXCLKN clock cycles, when it detects the framing patterns.
RXDATA[0:3] 66-63 LVDS output Receive data pins. Parallel data on this bus is valid on the falling edge of RXCLKP
P/N 60-57 (refer to Figure 6). RXDATA0 is the first bit received in time.
RXPARP 56 LVDS output Receive data parity output
RXPARN 55
TXDATA[0:3] 88-81 LVDS input Transmit data pins. Parallel data on this bus is clocked on the rising edge of TXCLKP.
P/N TXDATA0 is the first bit transmitted in time.
TXPARP 99 LVDS input Transmit data parity input
TXPARN 98
CONTROL/STATUS PINS
AUTO_DETECT 34 TTL input (with Data rate autodetect enable. Enable the autodetection function for different data rates.
pulldown) When AUTO_DETECT is high, the autodetection circuit generates RATEOUT0 and
RATEOUT1 to indicate the data rates for the downstream device.
CONFIG0 17 TTL input (with Configuration pins. Put the device under one of the four operation modes: TX only, RX
CONFIG1 18 pulldown) only, transceiver, or repeater. (See Table 3 )
ENABLE 44 TTL input (with Standby enable. When this pin is held low, the device is disabled for IDDQ testing.
pullup) When high, the device operates normally.
FRAME_EN 27 TTL input (with Frame sync enable. When this pin is asserted high, the frame synchronization circuit for
pullup) byte alignment is turned on.
LCKREFN 24 TTL input (with Lock to reference. When this pin is low, RXCLKP/N output is forced to lock to REFCLK.
pullup) When high, RXCLKP/N is the divided down clock extracted from the receive serial data.
LLOOP 53 TTL input (with Local loopback enable. When this pin is high, the serial output is internally looped back
pulldown) to its serial input.
LOL 45 TTL output Loss of lock. When the clock recovery loop has locked to the input data stream and the
phase differs by less than 100 ppm from REFCLK, then LOL is high. When the phase of
the input data stream differs by more than 100 ppm from REFCLK, then LOL is low. If
the difference is too large (> 500 ppm), the LOL output is not valid.
LOOPTIME 51 TTL input (with Loop timing mode. When this pin is high, the PLL for the clock synthesizer is bypassed.
pulldown) The recovered clock timing is used to send the transmit data.
LOS 46 TTL output Loss of signal. When no transitions appear on the input data stream for more than 2.3
µs, a loss of signal occurs and LOS goes high. The device also transmits all zeroes
downstream using REFCLK as its clock source. When a valid SONET signal is received,
the LOS signal goes low.
PAR_VALID 2 TTL output Parity checker output. The internal parity checker on the parallel side of the transmitter
checks for even parity. If there is a parity error, the pin is pulsed low for two clock
cycles.
4
Submit Documentation Feedback