Datasheet

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TIMING REQUIREMENTS
PLL PERFORMANCE SPECIFICATIONS
SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS
SERIAL DIFFERENTIAL SWITCHING CHARACTERISTICS
SLK2721
SLLS532B – JUNE 2002 – REVISED MARCH 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE CLOCK (REFCLK)
Frequency tolerance
(1)
–20 20 ppm
Duty cycle 40% 50% 60%
Jitter 12 kHz to 20 MHz 3 ps rms
Frequency range abosolute value 622.08 MHz
(1) The ± 20-ppm tolerance is required to meet SONET/SDH requirements. For non-SONET/SDH-compliant systems, looser tolerances may
apply.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLL startup lock time V
DD
, V
DDC
= 2.375 V, after REFCLK is stable 1 ms
Acquisition lock time Valid SONET signal or PRBS OC-48 2031 Bit Times
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PRE1 = 0, PRE2 = 0, Rt = 50,
650 850 1000
See Table 4 and Figure 1
Vodd = |STXDOP-STXDON|, transmit
PRE1 = 1, PRE2 = 0 550 750 900
differential output voltage under mV
de-emphasis
PRE1 = 0, PRE2 = 1 540 700 860
PRE1 = 1, PRE2 = 1 500 650 800
V
(CMT)
Transmit common mode voltage range Rt = 50 Ω 1100 1250 1400 mV
Receiver Input voltage requirement, 150 mV
Vid = |SRXDIP-SRXDIN|
V
(CMR)
Receiver common mode voltage range 1100 1250 2250 mV
Il Receiver input leakage –550 550 µ A
Rl Receiver differential impedance 80 100 120 Ω
CI Receiver input capacitance 1 pF
t
d(TX_Latency)
50
Bit Times
t
d(RX_Latency)
50
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
t
Differential signal rise time (20% to 80%) R
L
= 50 Ω 80 100 140 ps
t
j
Output jitter Jitter-free data, 12 kHz to 20 MHz, RLOOP = 0.05 0.1 UI
(pp)
1
1MHz 0.15 0.4
RLOOP = 1,
Jitter tolerance 100 kHz 1.5 4 UI
(pp)
See Figure 3
1 kHz 1.5 9
14
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