Datasheet
DS90UR916Q
www.ti.com
SNOSB46E –MARCH 2011–REVISED APRIL 2013
Deserializer DC Electrical Characteristics
(1)(2)(3)
(continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symb Parameter Conditions Pin/Freq. Units
Min Typ Max
ol
CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
Differential Output
V
OD
R
L
= 100Ω 542 mV
Voltage
Offset Voltage CMLOUTP,
V
OS
R
L
= 100Ω 1.4 V
Single-ended CMLOUTN
Internal Termination
R
T
80 100 120 Ω
Resistor
SUPPLY CURRENT
I
DD1
Checker Board Pattern, V
DD
= 1.89V All V
DD
pins 93 110 mA
OS_PCLK/DATA = H,
V
DDIO
=1.89V 33 45 mA
Deserializer
EQ = 001,
Supply Current
SSCG=ON,CMLOUTP/N
I
DDIO1
V
DDIO
(includes load current)
V
DDIO
= 3.6V 62 75 mA
enabled
C
L
= 4pF, Figure 4
V
DD
= 1.89V All V
DD
pins 40 3000 µA
I
DDZ
Deserializer Supply PDB = 0V, All other
V
DDIO
=1.89V 5 50 µA
Current Power Down LVCMOS Inputs = 0V
V
DDIO
I
DDIOZ
V
DDIO
= 3.6V 10 100 µA
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
PCLK Output Period PCLK 15.38 T 200 ns
t
RDC
PCLK Output Duty Cycle SSCG=OFF, 5–65MHz PCLK 43 50 57 %
SSCG=ON, 5–20MHz 35 59 65 %
SSCG=ON, 20–65MHz 40 53 60 %
t
CLH
LVCMOS V
DDIO
= 1.8V PCLK/RGB[7:0], HS, VS,
2.1 ns
Low-to-High C
L
= 4 pF (lumped load) DE
Transition Time, Figure 5
V
DDIO
= 3.3V
2.0 ns
C
L
= 4 pF (lumped load)
t
CHL
LVCMOS V
DDIO
= 1.8V PCLK/RGB[7:0], HS, VS,
1.6 ns
High-to-Low C
L
= 4 pF (lumped load) DE
Transition Time, Figure 5
V
DDIO
= 3.3V
1.5 ns
C
L
= 4 pF (lumped load)
t
ROS
Data Valid before PCLK – Set V
DDIO
= 1.71 to 1.89V or RGB[7:0], HS, VS, DE
Up Time, Figure 9 3.0 to 3.6V 0.27 0.45 T
C
L
= 4 pF (lumped load)
t
ROH
Data Valid after PCLK – Hold V
DDIO
= 1.71 to 1.89V or RGB[7:0], HS, VS, DE
Time, Figure 9 3.0 to 3.6V 0.4 0.55 T
C
L
= 4 pF (lumped load)
t
HBLANK
Horizontal Blanking Time HS 6 t
RCP
t
DDLT
Deserializer Lock Time, SSC[3:0] = 0000 (OFF)
(1)
PCLK = 5 MHz 3 ms
Figure 8
SSC[3:0] = 0000 (OFF)
(1)
PCLK = 65MHz 4 ms
SSC[3:0] = ON
(1)
PCLK = 5MHz 30 ms
SSC[3:0] = ON
(1)
PCLK = 65MHz 6 ms
t
DD
Des Delay - Latency, Figure 6 139*T 140*T ns
t
DPJ
(2)
Des Period Jitter SSC[3:0] = OFF
(3)(4)
PCLK = 5 MHz 975 1700 ps
PCLK = 10 MHz 500 1000 ps
PCLK = 65 MHz 550 1250 ps
(1) t
PLD
and t
DDLT
is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
(2) Specification is ensured by design and is not tested in production.
(3) t
DPJ
is the maximum amount the period is allowed to deviate over many samples.
(4) Specification is ensured by characterization and is not tested in production.
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