Datasheet
HOST
SER
or
DES
SCL
SDA
4.7k 4.7k
10 k
R
ID
SCL
SDA
To other
Devices
ID[X]
1.8V
V
DDIO
X XX
PCLK
(RFB = L)
BISTEN
(DES)
PASS
DATA
(internal)
PASS
BIST Duration
Prior Result
BIST
Result
Held
PASS
FAIL
X = bit error(s)
BISTEN
(SER)
RGB[7:0]
HS, VS, DE
DATA
(internal)
Case 1 - Pass Case 2 - Fail
Prior Result
Normal PRBS
BIST Test
Normal
DES Outputs
SER
DS90UR916Q
www.ti.com
SNOSB46E –MARCH 2011–REVISED APRIL 2013
Figure 26. BIST Waveforms
Optional Serial Bus Control
The DS90UR916 may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 27.
Figure 27. Serial Control Bus Connection
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to V
DDIO
. For most
applications a 4.7 k pull up resistor to V
DDIO
may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are
possible. The pin may be pulled to V
DD
(1.8V, NOT V
DDIO
)) with a 10 kΩ resistor; or a 10 kΩ pull up resistor (to
V
DD
1.8V, NOT V
DDIO
)) and a pull down resistor of the recommended value to set other three possible addresses
may be used. See Table 9. Do not tie ID[x] directly to VSS.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 28.
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