Datasheet

RIN-
DS90UR916Q ± DESERIALIZER
RIN+
Clock and
Data
Recovery
Timing and
Control
24
LOCK
PCLK
SSCG
Output Latch
Serial to Parallel
DC Balance Decoder
PASS
RGB [7:0]
HS
VS
DE
Error
Detector
PDB
BISTEN
CMF
SCL
SCA
ID[x]
STRAP INPUT
CONFIG [1:0]
LF_MODE
OS_PCLK/DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
MAPSEL [1:0]
STRAP INPUT
OP_LOW
FRC Dithering
1
White Balance LUT
FRC Dithering
2
R[7:0]
HS
VS
PCLK
PDB
Serializer Deserializer
DE
RGB Digital Display Interface
HOST
Graphics
Processor
FPD-Link II
1 Pair / AC Coupled
DS90UR905Q DS90UR916Q
100 ohm STP Cable
PASS
V
DDIO
PDB
SCL
SDA
CONFIG [1:0]
RFB
VODSEL
DeEmph
BISTEN
BISTEN
LOCK
ID[x]
DAP DAP
CMF
100 nF 100 nF
G[7:0]
B[7:0]
SCL
SDA
ID[x]
R[7:0]
HS
VS
PCLK
DE
G[7:0]
B[7:0]
STRAP pins
not shown
RIN+
RIN-
DOUT+
DOUT-
Optional Optional
(1.8V or 3.3V)
(1.8V or 3.3V)
1.8V
1.8V
V
DDIO
V
DDn
V
DDn
RGB Display
QVGA to XGA
24-bit or
18-bit dithered
color depth
DS90UR916Q
SNOSB46E –MARCH 2011–REVISED APRIL 2013 www.ti.com
Applications Diagram
Figure 1.
Block Diagrams
Figure 2.
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