Datasheet

PDB
1/2 V
DDIO
RIN
(Diff.)
PCLK,
RGB[7:0],
DE, HS, VS,
PASS, LOCK
"X"active
t
XZR
active Z (TRI-STATE)
23210
START
BIT
STOP
BIT
SYMBOL N+1
23210
START
BIT
STOP
BIT
SYMBOL N
RIN
(Diff.)
PCLK
(RFB = L)
t
DD
RGB[7:0],
HS, VS, DE
SYMBOL N-1 SYMBOL NSYMBOL N-2
80%
V
DDIO
20%
t
CLH
t
CHL
GND
GND
V
DDIO
GND
V
DDIO
RGB[n] (odd),
VS, HS
PCLK
w/ RFB = L
RGB[n] (even),
DE
GND
V
DDIO
DS90UR916Q
SNOSB46E –MARCH 2011–REVISED APRIL 2013 www.ti.com
AC Timing Diagrams and Test Circuits
Figure 4. Checkerboard Data Pattern
Figure 5. Deserializer LVCMOS Transition Times
Figure 6. Deserializer Delay – Latency
Figure 7. Deserializer Disable Time (OSS_SEL = 0)
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