Datasheet

DS90UR916Q
SNOSB46E –MARCH 2011–REVISED APRIL 2013 www.ti.com
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
DCCJ
(2)
Des Cycle-to-Cycle Jitter SSC[3:0] = OFF
(4)(5)
PCLK = 5 MHz 675 1150 ps
PCLK = 10 MHz 375 900 ps
PCLK = 65 MHz 500 1150 ps
t
RJIT
Des Input Jitter Tolerance, EQ = OFF, for jitter freq < 2MHz 0.9 UI
(6)
Figure 11 SSCG = OFF,
for jitter freq > 6MHz
0.5 UI
PCLK = 65MHz
BIST Mode
t
PASS
BIST PASS Valid Time,
1 10 ns
BISTEN = 1, Figure 12
SSCG Mode
f
DEV
Spread Spectrum Clocking PCLK = 5 to 65 MHz,
±0.5 ±2 %
Deviation Frequency SSC[3:0] = ON
f
MOD
Spread Spectrum Clocking PCLK = 5 to 65 MHz,
8 100 kHz
Modulation Frequency SSC[3:0] = ON
(5) t
DCCJ
is the maximum amount of jitter between adjacent clock cycles.
(6) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
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