Datasheet
24 SERDESUB-21USB User’s Guide SNLU101 – April 2012
Camera Mode:
In Camera mode, I
2
C transactions originate from the Master controller at the Deserializer
side. The I
2
C slave core in the Deserializer will detect if a transaction is intended for the
Serializer or a slave at the Serializer. Commands are sent over the bi-directional control
channel to initiate the transactions. The Serializer will receive the command and generate
an I
2
C transaction on its local I
2
C bus. At the same time, the Serializer will capture the
response on the I
2
C bus and return the response on the forward channel link. The
Deserializer parses the response and passes the appropriate response to the Deserializer
I
2
C bus.
Note: The default settings for this EVK are shipped with a display mode configuration, but
this EVK also supports a camera mode. This mode is suitable for setups where a camera
is connected to the DS90UB903Q Serializer end and a host controller is connected to the
DS90UB904Q Deserializer end. The I
2
C Master would need to be connected to the
DS90UB904Q Deserializer end. A typical setup for camera mode is shown below:
DS90UB904Q
Deserializer
SCL
SDA
MCU/FPGA
Host
PDB
RIN
+
-
ID[x]
PASS
LOCK
ROUT[20:0]
PCLK
1.8V
VDDIO
GPI0
VDDIO
MODE (M_S)
DS90UB903Q
Serializer
SCL
SDA
Camera
Module
PDB
VDDIO
DOUT
+
-
ID[x]
DIN[20:0]
PCLK
1.8V
VDDIO
GPO0
MODE (M_S), RES0
VDDIO
SCL
SDA
SCL
SDA
0xB0 0xC0
0xA0
BISTEN, RES0
VDD18
GPI1
GPI2
GPI3
GPO1
GPO2
GPO3
(3.3V I/O) (3.3V I/O)
1.0k 1.0k
00
10k 10k
1.0k1.0k
1.8V 3.3V 1.8V 3.3V
VDDIO
VDD18
VDDIO
DS90UB904Q
Deserializer
SCL
SDA
MCU/FPGA
Host
PDB
RIN
+
-
ID[x]
PASS
LOCK
ROUT[20:0]
PCLK
1.8V
VDDIO
GPI0
VDDIO
MODE (M_S)
DS90UB903Q
Serializer
SCL
SDA
Camera
Module
PDB
VDDIO
DOUT
+
-
ID[x]
DIN[20:0]
PCLK
1.8V
VDDIO
GPO0
MODE (M_S), RES0
VDDIO
SCL
SDA
SCL
SDA
0xB0 0xC0
0xA0
BISTEN, RES0
VDD18
GPI1
GPI2
GPI3
GPO1
GPO2
GPO3
(3.3V I/O) (3.3V I/O)
1.0k 1.0k
00
10k 10k
1.0k1.0k
1.8V 3.3V 1.8V 3.3V
VDDIO
VDD18
VDDIO
Figure 6. Example of DS90UB903Q/904Q in Camera Application