Datasheet

14 SERDESUB-21USB User’s Guide SNLU101 – April 2012
Configuration Settings for the Deserializer Demo Board
VDDIO: 1.8V or 3.3V LVCMOS INPUT/OUTPUT SELECTION
Reference Description +1.8V VDDIO +3.3V VDDIO JP12
JP12
VDDIO LVCMOS
I/O level configuration.
VDDIO = 1.8V
1.8V
LVCMOS
VDDIO = 3.3V
(Default)
apply external
3.3V LVCMOS
S1: Deserializer Input Features Selection
Reference Description Input = L Input = H S1
PDB PowerDown Bar Power
Down
(Disabled)
Operational
(Default)
BISTEN BIST Enable Pin Normal
operating
mode.
BIST is
disabled.
(Default)
BIST Mode is
enabled.
M_S
(MODE)
I
2
C Master / Slave
select
Master
(Default)
Slave
RES 0
(* IMPORTANT
See user note
below)
Reserved MUST be
tied low for
normal
operation
(Default)
*Note: In user layout RES0 MUST be tied low for proper operation.
1.8V
1.8V
3.3V