Datasheet

SNLU100 – April 2012 SERDESUB-16USB User’s Guide 7
DS9UB901Q Serializer Board Description:
The 2x17-pin IDC connector J1 accepts 16 bits of 1.8V or 3.3V data along with the PCLK
clock input. VDDI must be set externally for 1.8V or 3.3V LVCMOS inputs.
The Serializer board is powered externally from the J3 (VDD) and J4 (VSS) connectors
shown below. For the Serializer to be operational, the S1-PDB switch on S1 must be set
HIGH. S1-RES0 must be set LOW. Master or slave mode is user selected on S1-M_S
(MODE); please refer to DS90UB901/902 datasheet for details.
The USB connector P3 (USB-A side) on the bottom side of the board provides the
interface connection to the Deserializer board. Note: P2 (mini USB) on the top side is un-
stuffed and not to be used with the cable provided in the kit.
c P3 (BACKSIDE)
f J3, J4
JP1
c FPD-Link III I/O
d LVCMOS INPUTS
e FUNCTION CONTROLS
f
POWER SUPPLY
g INPUT TERMINATION
(For 50
Ω signal sources,
add 50
Ω termination, otherwise
leave unpopulated)
h I2C BUS CONTROL
i GPIO
J1 d
S1
e
g
g
g
g
c P2 (TOPSIDE)
(UNSTUFFED)
Note:
Connect cable
(USB A side)
to P2 on BACKSIDE.
1.8V
J6
,
JP8 h
J1 i
Note:
1) VDD and VSS MUST
be
applied externally from
here.
2) VDDI = 3.3V should be
applied separately on JP1
with default jumper on JP2
(VDDI=+3.3V),
otherwise jumper VDDI to
+1.8V