User’s Guide SNLU100 – April 2012 SERDESUB-16USB User’s Guide Table of Contents TABLE OF CONTENTS..................................................................................................................................... 1 INTRODUCTION:............................................................................................................................................... 2 CONTENTS OF THE DEMO EVALUATION KIT: ..................................................................................
Introduction: Texas Instruments’ Automotive Serdes DS90UB901Q/902Q FPD-Link III evaluation kit contains one (1) DS90UB901Q Serializer board, one (1) DS90UB902Q Deserializer board, and one (1) two (2) meter* high speed USB 2.0 cable. *Note: the chipset can support up to ten (10) meters. The DS90UB901Q/902Q chipset supports a variety of automotive vision applications over a two (2) wire serial stream.
System Requirements: In order to demonstrate, the following are required: 1) Video source with 1.8V or 3.3V LVCMOS parallel interface 2) Microcontroller (MCU) or FPGA with I2C interface bus (I2C master) a. slave clock stretching must be supported by the I2C master controller/MCU. 3) External peripheral device that supports I2C (slave mode) 4) Power supply for 1.8V (required) and 3.
Camera Module (Video Data + Ctrl) DS90UB901Q Serializer (I2C_CTRL) FPD-LINK III DS90UB902Q Deserializer (I2C_CTRL) (Video Data + Ctrl) Host Controller / FPGA / Video Processor LCD Display Figure 2. Typical DS90UB901Q/902Q Camera System Diagram Figure 1 and Figure 2 illustrate the use of the Chipset (Serializer/Deserializer) in a Camera to Host (MCU/FPGA) Controller. Refer to the proper datasheet information on Chipsets (Serializer/Deserializer) provided on each board for more detailed information.
How to set up the Demo Evaluation Kit: The DS90UB901Q/902Q evaluation boards consist of two sections. The first part of the board provides the point-to-point interface for transmitting parallel video data. The second part of the board allows bi-directional control communication of an I2C bus control of using a MCU/FPGA to programming a remote peripheral device via the Deserailizer. The PCB routing for the Serializer input pins (DIN) accept incoming parallel video data at 1.8V/3.
Bi-Directional Control Bus And I2C Modes: In order to communicate and synchronize with remote devices on the I2C bus through the bi-directional control channel, slave clock stretching must be supported by the I2C master controller/MCU. The chipset utilizes bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low prior to the 9th clock of every I2C data transfer (before the ACK signal).
DS9UB901Q Serializer Board Description: The 2x17-pin IDC connector J1 accepts 16 bits of 1.8V or 3.3V data along with the PCLK clock input. VDDI must be set externally for 1.8V or 3.3V LVCMOS inputs. The Serializer board is powered externally from the J3 (VDD) and J4 (VSS) connectors shown below. For the Serializer to be operational, the S1-PDB switch on S1 must be set HIGH. S1-RES0 must be set LOW. Master or slave mode is user selected on S1-M_S (MODE); please refer to DS90UB901/902 datasheet for details.
Configuration Settings for the Serializer Demo Board VDDI: 1.8V or 3.3V LVCMOS INPUT/OUTPUT SELECTION Reference Description +1.8V VDDI +3.3V VDDI VDDI LVCMOS VDDI = 3.3V JP2 VDDI = 1.8V I/O level configuration. (Default) JP1 NOT USED 1.8V 1.8V LVCMOS inputs JP2 1.8V apply external 3.
JP4,VR3: Address Decoder Reference Description DS90UB901Q JP4 I2C Device ID Address Selection Default address: 0xB0’h JP4 & VR3 RID value adjustment (via screw) JP4 MUST have a jumper to use VR3 potentiometer.
Table 1. ID[x] Resistor Value – DS90UB901Q Slave Address Address 8'b Rid Resistor Ω Address 7'b 0 appended (WRITE) 0 7b' 101 1000 (h'58) 8b' 1011 0000 (h'B0) 2.0K 7b' 101 1001 (h'59) 8b' 1011 0010 (h'B2) 4.7K 7b' 101 1010 (h'5A) 8b' 1011 0100 (h'B4) 8.2K 7b' 101 1011 (h'5B) 8b' 1011 0110 (h'B6) 12.1K 7b' 101 1100 (h'5C) 8b' 1011 1000 (h'B8) 39.
JP6, JP7: USB Red and Black wire Reference Description Power wire in USB cable JP6 thru P3 (and P2 not mounted) connector Jumper RED to VSS – recommended VDD VSS Red wire tied Red wire tied to VSS to VDD (Default) OPEN Red wire floating (not recommended) JP6 JP6 JP6 Black wire tied to VDD Black wire tied to VSS (Default) Black wire floating (not recommended) JP7 JP7 JP7 Note: Normally VDD in USB application Power wire in USB cable thru P3 (and P2 not mounted) connector Jumper BLACK to VSS – rec
Serializer LVCMOS and FPD-Link III Pinout by Connector The following three tables illustrate how the Serializer connections mapped to the IDC connector J1, the FPD-Link III I/O on the USB-A connector P3, and the mini USB P2 (not mounted) pinouts. Note – labels are also printed on the demo boards for both the LVCMOS inputs/outputs and FPD-Link III I/Os. J1 LVCMOS I/O pin no. name name pin no.
DS9UB902Q Deserializer Board Description: The USB connector J2 (mini USB) on the topside of the board provides the interface connection for FPD-Link III signals to the Serializer board. Note: J11 (mini USB) on the bottom side is un-stuffed and not used with the cable provided in the kit. The Deserializer board is powered externally from the J4 (VDD) and J5 (VSS) connectors shown below. For the Deserializer to be operational, the S1 switch – PDB must be set HIGH.
Configuration Settings for the Deserializer Demo Board VDDIO: 1.8V or 3.3V LVCMOS INPUT/OUTPUT SELECTION Reference Description +1.8V VDDIO +3.3V VDDIO VDDIO LVCMOS JP2 VDDIO = 1.8V VDDIO = 3.3V I/O level configuration. (Default) 1.8V 1.8V 1.8V LVCMOS S1: Deserializer Input Features Selection Reference Description Input = L PDB PowerDown Bar Power Down (Disabled) BISTEN BIST Enable Pin Normal operating mode. BIST is disabled.
JP8,VR3: Address Decoder Reference Description DS90UB902Q JP8 I2C Device ID Address Selection Default address: 0xC0’h RID value adjustment (via screw) JP8 MUST have a jumper to use VR3 potentiometer.
Deserializer Bidirectional Control Bus (SCL, SDA) - I2C Compliant Reference Description Settings J8 Pinout: I2C Port 1 – VDD_I2C 2 – SCL 3 – SDA 4 – VSS JP9 16 I2C Input Port SERDESUB-16USB User’s Guide Closed: VDD_I2C power is applied through the VDDIO source with onboard 1.0Kohm pull up resistors (Default) Connector Open: VDD_I2C power is applied externally Note: when connecting the bus externally, the target source must have external pull up resistor.
JP5: Output Lock Monitor Reference Description LOCK Receiver PLL LOCK Note: DO NOT SHORT JUMPER IN JP5. JP4: Output Pass Monitor Reference Description PASS PASS (CRC / BIST modes) Note: DO NOT SHORT JUMPER IN JP4.
Deserializer FPD-Link III Pinout and LVCMOS by Connector The following three tables illustrate how the Deserializer connections mapped to the IDC connector J7, the mini USB connector J2, and the mini USB connector J11 pinouts. Note – labels are also printed on the demo boards for both the FPD-Link III I/O and LVCMOS inputs/outputs. J7 pin no. 18 LVCMOS I/O name name pin no. J2 (topside) FPD-Link III J11 (bottom side) (not mounted) 1 GPIO[0] GND 2 pin no. name 3 GPIO[1] GND 4 1 JP6 pin no.
Typical Connection and Test Equipment The following is a list of typical test equipment that may be used to generate signals for the Serializer inputs: 1) Digital Video Source – for generation of specific display timing such as CMOS imager or Graphics Controller with digital video signals (1.8V/3.3V LVCMOS). 2) Any other signal generator / video source that generates the correct input levels.
Evaluation of the Bi-directional Control Channel VDDIO VDD18 VDDIO VDD18 This section describes how to perform I2C instructions between MCU/FPGA and a remote peripheral device through the DS90UB902Q and DS90UB901Q pair configured in a camera type of application. Figure 4 shows the configuration of evaluation boards for I2C communication. A MCU/FPGA controller with an I2C interface is required. Refer to the DS90UB901Q/902Q datasheet for the definition of each register. SCL SDA Figure 4.
Procedure - Camera Mode: 1) Connect the 1.8V and 3.3V power with +1.8V and +3.3V supplies accordingly. Keep the power off. 2) Verify that all the jumper positions and switches are correctly set (as per default positions defined in “Configuration Settings for the Serializer/Deserializer Demo Board” tables). 3) Connect the USB interface cable between P3 (DS90UB901Q board) connector and J2 connector (DS90UB902Q board).
b. DS90UB902Q Deserializer (0xC0) i. Write 0x04 to Register 0x01 1. Verify that LOCK LED2 is lit; This indicates the chipset is Locked 9) After initialization, the camera PCLK clock and input data can begin transmission to the Serializer. The Serializer locks onto PCLK input (if present) otherwise the onchip oscillator (25 MHz) is used as the input clock source. Note the MCU controller should monitor the LOCK pin and confirm LOCK = H before performing any I2C communication across the link. Figure 5.
5) Host controller to load and transmit write transaction to register byte 0x13 = 0xFF. Note default of register 0x13 = 0x00. 6) Host controller to read back Serializer 0xB0 register 0x13 = 0xFF Figure 6.
Display Mode: In Display mode, I2C transactions originate from the controller attached to the Serializer. The I2C slave core in the Serializer will detect if a transaction targets (local) registers within the Serialier or the (remote) registers within the Deserializer or a remote slave connected to the I2C master interface of the Deserializer. Commands are sent over the forward channel link to initiate the transactions.
Procedure - Display Mode: 1) Connect the 1.8V and 3.3V power with +1.8V and +3.3V supplies accordingly. Keep the power off. 2) Verify that all the jumper positions and switches are correctly set. NOTE: For Display Mode, the default settings for switch S1-M_S on S1 for the DS90UB901Q Serializer and DS90UB902Q Deserializer boards must be reversed. DS90UB901Q board: S1 DS90UB902Q board: S1 3) Connect the USB interface cable between P3 (DS90UB901Q board) connector and J2 connector (DS90UB902Q board).
1. Verify that LOCK LED2 is lit; This indicates the chipset is Locked 8) After initialization, the PCLK clock and input data can begin transmission to the Serializer. The Serializer locks onto PCLK input (if present) otherwise the on-chip oscillator (25 MHz) is used as the input clock source. Note the user should monitor the LOCK pin and confirm LOCK = H before performing any I2C communication across the link. Figure 8.
6) Host controller to read back Deserializer 0xC0 register 0x13 = 0xFF Configuration: Serializer: ADDR = 0xB0h Slave mode (MODE = H); PDB=H START Deserializer: ADDR: 0xC0h Master mode (MODE = L); BISTEN=L, PDB=H LOCK = H Read data from 0xB0 Write/Verify 0xB0 Reg 0x06 = 0xC0 NO Register 0x06 = 0xC0 Read Deserializer Register 0x06 SER DEV ID Write command to Deserializer Reg 0x06 SER DEV ID YES Read data from 0xC0 NO Register 0x13 = 0x00 Send Read command to Serializer Reg 0x13 GPCR Read Back Seria
Troubleshooting Demo Setup NOTE: The DS9UB901Q and DS9UB902Q are NOT USB compliant and should not be plugged into a USB device nor should a USB device be plugged into the demo boards. If the demo boards are not performing properly, use the following as a guide for quick solutions to potential problems. If the problem persists, please contact the local Sales Representative for assistance. QUICK CHECKS: 1. Check that Powers and Grounds are connected to both Serializer and Deserializer boards. 2.
Note: Please note that the following references are supplied only as a courtesy to our valued customers. It is not intended to be an endorsement of any particular equipment or supplier. Cable References The FPD-Link III interface cable included in the kit is a standard off-the-shelf high-speed USB 2.0 with a 4-pin USB A type on one end and a 5-pin mini USB on the other end and is included for demonstration purposes only.
Appendix Serializer and Deserializer Demo PCB Schematics: 30 SERDESUB-16USB User’s Guide SNLU100 – April 2012
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BOM (Bill of Materials) Serializer Demo PCB: DS90UB901 Tx Demo Board - Board Stackup Revised: Tuesday, July 27, 2010 DS90UB901 Tx Demo Board Revision: 1B Bill Of Materials Item Quantity Reference Part ______________________________________________ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 2 4 2 6 2 6 5 2 3 5 1 1 1 2 1 1 2 1 1 1 18 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1 1 4 1 2 1 1 4 2 1 1 1 2 1 1 2 2 1 2 1 C1,C12 C13,C2 C3,C4,C8,C9 C5,C6 C7,C16,C19,C20,C23,C27 C1
BOM (Bill of Materials) Deserializer Demo PCB: DS90UB902 Rx Demo Board - Board Stackup Revised: Tuesday, July 27, 2010 DS90UB902 Rx Demo Board Revision: 1B Bill Of Materials Part Item Quantity Reference ______________________________________________ 40 1 2 3 4 5 6 7 4 1 4 2 2 2 21 8 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 6 6 2 3 4 2 1 1 1 1 2 1 1 1 2 1 1 1 1 2 1 5 1 2 1 6 2 2 1 2 1 1 2 2 1 2 C1,C2,C6,C7 C3 C4,C5,C12,C13 C8,C11 C9,
Serializer (Tx) Demo PCB Layout: SNLU100 – April 2012 SERDESUB-16USB User’s Guide 41
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Serializer (Tx) Demo PCB Stackup: 44 SERDESUB-16USB User’s Guide SNLU100 – April 2012
Deserializer (Rx) Demo PCB Layout: SNLU100 – April 2012 SERDESUB-16USB User’s Guide 45
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Deserializer (Rx) Demo PCB Stackup: 48 SERDESUB-16USB User’s Guide SNLU100 – April 2012
FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general customer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.
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