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EMI Mitigation Features

7 EMI Mitigation Features

The differential LVDS style physical layer is used to help minimize the generation of EMI. Line driver

transition times are controlled to be balanced and centered. This is done to minimize any common-mode

currents from the line driver. The odd-mode (differential) signaling generates equal and opposite currents

in the pair which also help to lower overall emissions. The serial link is terminated at both the source and

load ends to minimize any signal reflections. Certain parts provide internal terminations to reduce external

part count and to also minimize the resulting stub lengths.

The Parallel Bus at the DES (receiver output) is also optimized to reduce EMI. Edge rates are controlled,

and on certain DES devices an output drive strength control is provided. Most DES devices support PTO

(progressive turn-on), a feature that groups the data outputs into banks and offsets the switching point in

time to reduce simultaneous switching and thus reduce supply noise. Other devices employ frequency

spread PTO to dynamically alter the output switching sequence and further enhance the noise reduction of

the wide bus. Spread spectrum clock generation is provided by some deserializers. This feature

modulates the output clock and data period to effectively spread the energy associated with periodic

output transitions and minimize emissions.

8 Current FPD-Link II SerDes Devices

Many variants of FPD-Link II SER and DES devices are currently available with more to follow.

Table 1. Select FPD-Link II SER and DES Device Comparison Table

Color Depth General

NSID (root) Function Parallel Interface PCLK (MHz)

(bits per pixel) Purpose I/O

DS90C241Q SER 18-bit 3 LVCMOS 5 to 35

DS90C124Q DES 18-bit 3 LVCMOS 5 to 35

DS90UR241Q SER 18-bit 3 LVCMOS 5 to 43

DS90UR124Q DES 18-bit 3 LVCMOS 5 to 43

DS99R421Q SER 18-bit 3 FPD-Link (3D + C LVDS) 5 to 43

DS90UR905Q SER 24-bit N/A LVCMOS 5 to 65

DS90UR906Q DES 24-bit N/A LVCMOS 5 to 65

DS90UR907Q SER 24-bit N/A FPD-Link (4D + C LVDS) 5 to 65

DS90UR908Q DES 24-bit N/A FPD-Link (4D + C LVDS) 5 to 65

Check website for latest product introductions.

9 Summary

The FPD-Link II SerDes devices provide an embedded clock single serial stream for Display, Imaging,

Pixel based, and other applications. The serial interface greatly eases interconnect design in terms of

space, pins, skew and cost. The FPD-Link II DES devices with the special clock recovery circuitry are

unique in that they do not require training patterns, a local reference clock, and support hot-plugging into a

live link.

SNLA102B–May 2008–Revised April 2013 AN-1807 FPD-Link II Display SerDes Overview

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