Datasheet

C1
b0
b1 b2 b3 b4 b6b5 b7 b8 b9 Bb10 b11 A b12 b13 b14 b15 b16
b17 b18 b19 b20 b21
b22 b23 C0
T
PCLK
RED
GREEN
BLUE
VSYNC
HSYNC
DE
GP0
GP1
GP2
PCLK
PLL
CONFIG.
RED
GREEN
BLUE
VSYNC
HSYNC
DE
GP0
GP1
GP2
PCLK
CONFIG.
Input Latch
Encoding
Parallel to Serial
TX
Serial to Parallel
Output Latch
RX
Decoding
PHY
control
PHY
control
CDR
/
PLL
FPD-Link II SERIALIZER FPD-Link II DESERIALIZER
24-Bit LVCMOS
24-Bit LVCMOS
Introduction www.ti.com
1 Introduction
The FPD-Link II SerDes family serializes the wide parallel display bus all the way to a single serial
differential signal as shown in Figure 1. Signal compression ratios of 24:1 or even greater (if ground wires
are taken into account) are obtained. Current devices in the family support common 18-bit and 24-bit RGB
Display applications. With the single serial signal, skew problems between multiple lines (lanes) are
removed and cable lengths up to 10 meters are supported. This makes the FPD-Link II SerDes ideal for
long reach applications with low cost small cables.
The single serial differential signal carries the parallel data (RGB and control) information, clock
information and a small amount of serial overhead. Routing of the single signal pair greatly eases system
design, saves bulk interconnect, saves connector pins, and reduces concern over interface interconnect
skew.
Figure 1. General Block Diagram – FPD-Link II 18-bit RGB Display Application
An example of the 24-bit (user) payload is shown in Figure 2. The 24-bit data field is appended with four
additional serial bits which provide the embedded clock information, link coding, and operating mode
information. A fixed clock edge is created between the C0 and C1 bits, and the coding/mode information is
conveyed by the A and B bits.
Figure 2. 24-bit Serial Payload Example
2
AN-1807 FPD-Link II Display SerDes Overview SNLA102B–May 2008–Revised April 2013
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