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Application Report

SNLA102B–May 2008–Revised April 2013

AN-1807 FPD-Link II Display SerDes Overview

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ABSTRACT

TI’s FPD-Link II family of embedded clock LVDS SerDes provide enhanced features, and improved signal

quality over prior generations of FPD-Link SerDes devices for Display applications. FPD-Link Chipsets

serialized the wide parallel RGB buses down to 4 or 5 pairs of LVDS signaling depending upon the

chipset. 18-bit RGB was serialized to three LVDS data lines and a LVDS clock, while 24-bit RGB was

serialized to four LVDS data lines and a LVDS clock. This provided a smaller, higher speed video bus and

has become the defacto standard for Notebook Display interfaces.

Contents

1 Introduction .................................................................................................................. 2

2 The SERIALIZER Function ................................................................................................ 3

3 The DESERIALIZER Function ............................................................................................ 3

4 Serial Payload ............................................................................................................... 3

5 Streaming RGB Display Applications .................................................................................... 4

6 Signal Quality Enhancers .................................................................................................. 4

7 EMI Mitigation Features .................................................................................................... 5

8 Current FPD-Link II SerDes Devices ..................................................................................... 5

9 Summary ..................................................................................................................... 5

List of Figures

1 General Block Diagram – FPD-Link II 18-bit RGB Display Application.............................................. 2

2 24-bit Serial Payload Example ............................................................................................ 2

3 24-bit RGB FPD-Link II SERDES XGA Display Application........................................................... 4

List of Tables

1 Select FPD-Link II SER and DES Device Comparison Table......................................................... 5

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SNLA102B–May 2008–Revised April 2013 AN-1807 FPD-Link II Display SerDes Overview

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Summary of content (6 pages)

PAGE 1
Application Report SNLA102B – May 2008 – Revised April 2013 AN-1807 FPD-Link II Display SerDes Overview ..................................................................................................................................................... ABSTRACT TI’s FPD-Link II family of embedded clock LVDS SerDes provide enhanced features, and improved signal quality over prior generations of FPD-Link SerDes devices for Display applications.
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Introduction 1 www.ti.com Introduction The FPD-Link II SerDes family serializes the wide parallel display bus all the way to a single serial differential signal as shown in Figure 1. Signal compression ratios of 24:1 or even greater (if ground wires are taken into account) are obtained. Current devices in the family support common 18-bit and 24-bit RGB Display applications.
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The SERIALIZER Function www.ti.com 2 The SERIALIZER Function The Serializer (SER) function generically collects a wide parallel bus plus its clock signal, performs payload optimization, appends the serial control bits and level translates the high-speed serial signal to LVDS-like levels. The payload is optimized for serial transmission over AC-coupled interconnects. This step balances the data being sent to support the AC-coupled transmission.
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Streaming RGB Display Applications 5 www.ti.com Streaming RGB Display Applications The FPD-Link II chipset is mainly used for RGB applications with various display resolutions. With the basic chipset (DS90UR241/124), 18-bit color depth is commonly used. A wide range of PCLK rates are supported depending upon the chipset selected. Of the user data payload, that is, the 24 data bits, 18 bits of RGB information, 3 display control signals (HS, VS, DE) and 3 general purpose signals are sent per PCLK.
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EMI Mitigation Features www.ti.com 7 EMI Mitigation Features The differential LVDS style physical layer is used to help minimize the generation of EMI. Line driver transition times are controlled to be balanced and centered. This is done to minimize any common-mode currents from the line driver. The odd-mode (differential) signaling generates equal and opposite currents in the pair which also help to lower overall emissions.
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