LMH1983 Evaluation Kit Users Guide LMH1983 Evaluation Kit Users Guide Version 1.
LMH1983 Evaluation Kit Users Guide INTRODUCTION The LMH1983 Evaluation Kit (EVK) allows for the evaluation of the LMH1983 3G/HD/SD Video Clock Generator with Audio Clock. The LMH1983 device is configured and controlled using National Semiconductor’s Analog Launch Pad (ALP) software graphical user interface (GUI). The GUI with the LMH1983 profile runs on Windows PC and can be used to program the device’s control registers through the I2C interface.
LMH1983 Evaluation Kit Users Guide LMH1983 EVALUATION BOARD OVERVIEW The following block diagram shows an overview of the LMH1983 evaluation board and general location of the main features, which will be discussed in the following sections of this manual. Power Header Power LEDs J8 LP 3878 CLKout1 SMA LPF Analog Ref. In BNC J1 LMH 1981 J2 Syncs Quad 2:1 MUX VCXO X1 J4 HVF inputs CLKout2 SMA J5 LMH1983 CLKout3 SMA J6 EXT.
LMH1983 Evaluation Kit Users Guide Installing the software: The evaluation kit contains a CD which has the control software on it. Running the program on the CD will install the software on your computer. Apply power to the Evaluation Board, and then attach a USB cable between the computer and the board.
LMH1983 Evaluation Kit Users Guide Select “Install from a list or specific location” Page 5 of 25
LMH1983 Evaluation Kit Users Guide Page 6 of 25
LMH1983 Evaluation Kit Users Guide For the location, enter “C:\Program Files\National Semiconductor Corp\Analog Launchpad Vxxx\DRIVERS” This directory was installed on your computer during the ALP software installation. The computer will warn you that the software has not passed Windows Logo Testing. Go ahead and Continue Anyway. The driver for the LMH1983 evaluation board will now be installed, and you can start the ALP software.
LMH1983 Evaluation Kit Users Guide The status indications on the GUI are only updated when the Read Controls/Status button is clicked. To have continuous updates, click the checkbox ‘Auto Refresh Status’, I also like to check the ‘Perform ReadAll after write’ box – this will update all of the status controls whenever something is written. In some cases, writing to one register will result in multiple things changing, and checking this button will make sure that everything is kept updated.
LMH1983 Evaluation Kit Users Guide I2C SLAVE ADDRESS The I2C address select jumper JP9 (3-way) can be configured as follows to select one of the three I2C slave addresses offered by the LMH1983. The default for the board, and for the ALP software is address ‘66h which corresponds to no jumper installed.
LMH1983 Evaluation Kit Users Guide o 625i/25 o 625p/50 o 720p/23.98/24/25/29.97/30/50/59.94/60 o 1080i/25/29.97/30 o 1080p/23.98/24/25/29.97/30/50/59.94/60 o 1080pSf/23.98/24/25/29.97/30 Audio Word Clock o 32 kHz, 48 kHz, 96 kHz, 44.1 kHz System Clock o 27 MHz o 10 MHz Configuring the board for operation with a digital video reference signal An external digital reference signal, consisting of H,V and F may be applied to J2, a jumper should installed on JP5, and the jumper on JP3 should be removed.
LMH1983 Evaluation Kit Users Guide Page 11 of 25
LMH1983 Evaluation Kit Users Guide PLL1 LOOP FILTER AND VCXO The LMH1983’s primary phase lock loop, PLL1, provides the following key functions: Synchronizes the 27 MHz VCXO clock to the reference input Attenuates (cleans) input jitter Provides a stable, low-jitter 27 MHz clock for PLLs 2, 3, 4 The external loop filter and 27 MHz VCXO are essential to the performance of PLL1, which dominates the overall loop response of the LMH1983.
LMH1983 Evaluation Kit Users Guide Figure 1: Loop Filter and LMP7711 Buffer Schematic Op Amp Buffer The LMP7711 Precision, Low-Noise Op Amp (U4) is used as a buffer to isolate the relatively low input impedance of the VCXO, which would otherwise be the dominant source of leakage current for loop filter circuit. The op amp offers very high input impedance to minimize this leakage current and high slew rate to ensure proper loop operation.
LMH1983 Evaluation Kit Users Guide VCXO The 27 MHz VCXO (X2) is specified for ±50 ppm APR (min) and ±50 ppm frequency stability. The calculated VCXO gain is 1000 Hz/V (min). The VCXO gain parameter (KVCO) affects the PLL1 loop response, so it must be considered when designing the nominal loop bandwidth and damping factor. The VCXO’s single-ended output clock can be measured at TP26 (XOclk+). The VCXO clock is received at the XOin+ input of the LMH1983.
LMH1983 Evaluation Kit Users Guide Appendix A Schematics Page 15 of 25
1 2 3 4 5 6 A A VDD_CLK1 VDD_CLK2 VDD_CLK3 VDD_PLL34 Layout Note: Unless otherwise noted, label all ICs, Test Points, Jumpers and Headers per the component comment. For jumpers and headers, label pins according to the pin legend noted. All labels should be present on top and bottom silk screen (except for ICs).
1 2 3 4 5 6 VDD A CLKout1_P COC49 C49 NLCLKout10P CLKout1_P PIC4901 PIC4902 COR60 R60 PIR6001 6 PIU506 COJP13 JP13 10 PIU5010 PIR6002 100 ENABLE SD/HD 1 PIU501 SDI 2 PIU502 SDI COC50 C50 NLCLKout10N CLKout1_N 4 PIU504 PIC5301 COC53 C53 PIC5302 0.
1 2 3 4 5 6 Analog Input and LMH1981 Sync Separator COU1 U1 COR1 R1 PIR102 COTP1 TP1 COC1 C1 VIDEO IN A COJ1 J1 COR3 R3 PIJ101 Ref. In PIJ1032 COJP1 JP1 PIR302 2 PIJP102 PIC102 PITP101 PIR301 0 2 PIJP202 1 PIJP101 PIC202 PIC702 PIC901 PIC902 LPF ENAB 75.0 2 PIU102 VCC 3 PIU103 PIC201 0.1uF PIC701 COC8 C8 1 PIJP201 COR4 R4 75R TERM PIR402 PIU101 COC2 C2 PIC101 1uF COC7 C7 COJP2 JP2 PIR401 1 PIR101 10.0k 1% OPEN PIC802 COC9 C9 0.
1 2 3 4 Power Supply Input and Low-Noise 3.3V LDO Regulator A COD4 D4 Layout Note: Unless otherwise noted, label all ICs, Test Points, Jumpers and Headers per the component comment. For jumpers and headers, label pins according to the pin legend noted. All labels should be present on top and bottom silk screen (except for ICs).
1 2 3 4 A A VDD COU10 U10 COP2 P2 COP1 P1 6 5 4 3 2 1 10 11 PIU10011 12 PIU10012 13 PIU10013 14 PIU10014 15 PIU10015 16 PIU10016 17 PIU10017 PIP206 PIU10010 PIP205 PIP204 PIP203 PIP202 PIP201 Header 6 GND SCL SDA B VDD PIR8602 COJ9 J9 0.
CODesignator1 COJP17 PAJP1701 PAJP1702 COC74 COU9 PAU901 PAU902 COC68 PAU908 PAU909 PAU904 PAR8501 PAR8502 PAC9001 PAC9002 COTP30 PAC7102 PAC7101 COJP18 PAJP201 PAJP202 PAR302 PAR301 COR3 COJP3 COC2 PATP101 PAC102 PAC9301 PAC9302 PAC9401 PAC9402 COTP28 COTP29 COC42 COC43 PATP3101 PATP2901 PAC202 PAC201 PAC101 PAC801 PAC802 PAL302 PAC1501 PAL301 PAC1502 PAC1701 PAC1601 PAC1702 PAC1602 COC16 COJ2 PASW102 COTP3 COSW1 PATP301 PAR2002 COR20 PAR2001 PAR2003 PAC1401 PAC1402 PAU
PAR8401 PAR8402 COR84 COC49 COR50 COR48 PAR5002 PAR5001 PAL402PAL401 PAL402 PAL401 PAC4501 PAC4502 PAC4901 PAC4902 PAR5802 PAR5801 COC50 PAC50 1 PAC50 2 PAC4 01 PAC4402 COC44 COL4 PAR4801 PAR4802 COR58 PAR6102PAR6101 COR61 COC45 PAC4102 PAC4101 COC41 PAC4602 PAC4601 COC46 COR7 COC13 PAC1302PAC1301 COC12 PAC1202 PAC1201 COL2 COC11 PAC1101 PAC1102 COC10 PAC1001 PAC1002 COC7 PAU2016 PAU2015 PAU2014 PAU2013 COR29 PAU2012 PAU2011 PAU2010 PAU209 PAU205 PAU206 PAU207 PAU208 COU2 COR33 COC75
CODesignator1 COJP17 PAJP1701 PAJP1702 COC74 COR81 COC73 COC69 COD5 COR84 PAC7401 PAC7402 COU9 PAU901 PAU902 COC68 PAR8102 PAR8101 PAD602 PAD501 PAD601 COTP6 COR82 PAR8202 PAR8201 PAU909 PAU907 PAU904 PAU905 COR83 COC90 COC91 COC92 PAR8302 COR85 COR80 PAC7002 PAR8002 PAR8001 PAC7001 PAC6902 PAC6901 PATP601 PAR8501 PAR8502 PAC9001 PAC9002 COTP30 PATP2801 COC70 COC71 COC72 PATP3001 COTP5 COJP18 COC93 COC94 PATP501 PAC7102 PAC7101 PAC7202 PAC7201 PAC9101 PAC9201 PAJP1802 PAJP1801
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
