Low Phase Noise Clock Evaluation Board User's Guide

List of Figures
1 CDCE421EVM Evaluation Board .......................................................................................... 5
2 CDCE421EVM Programming Blocks...................................................................................... 6
3 Software Installation Screen ................................................................................................ 8
4 Installation Prompt ........................................................................................................... 8
5 TI Chronos Software GUI ................................................................................................... 9
6 Chronos GUI—Loop Filter Configuration Pop-Up ...................................................................... 10
7 Chronos GUI—Manual PLL Block Selection Pop-Up .................................................................. 11
8 JP1 Setting for USB Programming Configuration ...................................................................... 13
9 CDCE421EVM Block Switch Off ......................................................................................... 14
10 CDCE421EVM Board Schematic ........................................................................................ 15
11 CDCE421EVM Board—Block A Schematic ............................................................................ 16
12 CDCE421EVM Board—Block B Schematic ............................................................................ 17
13 CDCE421EVM Board—Block C Schematic ............................................................................ 18
14 CDCE421EVM Board—Block D Schematic ............................................................................ 19
4 List of Figures SCAU020 – March 2007
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