Datasheet

16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
A0
A1
A2
A3
A4
A5
A6
A7
DAP
(GND)
TDO
TDI
TMS
TCK
TRST
V
DD
VREF
V
DD
SCANSTA476
SNLS171G –JANUARY 2005–REVISED APRIL 2013 www.ti.com
Connection Diagram
Figure 1. DAP = GND
(Top View)
Pin Descriptions
Pin No. Symbol Description
ANALOG I/O
16 A0 Analog input 0. This signal can range from 0V to V
REF
.
15 A1 Analog input 1. This signal can range from 0V to V
REF
.
14 A2 Analog input 2. This signal can range from 0V to V
REF
.
13 A3 Analog input 3. This signal can range from 0V to V
REF
.
12 A4 Analog input 4. This signal can range from 0V to V
REF
.
11 A5 Analog input 5. This signal can range from 0V to V
REF
.
10 A6 Analog input 6. This signal can range from 0V to V
REF
.
9 A7 Analog input 7. This signal can range from 0V to V
REF
.
2 V
REF
Analog reference voltage input. V
REF
must be ≤ V
DD
. This pin should be connected to a quiet source
(not directly to V
DD
) and bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1
cm of the V
REF
pin.
DIGITAL I/O
6 TDI Test Data Input to support IEEE 1149.1 features
5 TDO Test Data Ouput to support IEEE 1149.1 features
7 TMS Test Mode Select to support IEEE 1149.1 features
8 TCK Test Clock to support IEEE 1149.1 features
4 TRST Test Reset to support IEEE 1149.1 features
POWER SUPPLY
Positive supply pin. These pins should be connected to a quiet +2.7V to +5.5V source and bypassed to
1,3 V
DD
GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin.
Ground reference for CMOS circuitry. DAP is the exposed metal contact at the bottom of the WSON
See
(1)
GND package. The DAP is used as the primary GND connection to the device. It should be connected to the
ground plane with at least 4 vias for optimal low-noise and thermal performance.
(1) Note that GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the WSON package.
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