Datasheet

STA112 STA112 STA112 STA112 STA112 STA112
Backplane IEEE
1149.1
Test Bus
ASIC
with
JTAG
Backplane
IEEE 1149.1
Test Bus
Buffer with
JTAG
Buffer with
JTAG
Buffer with
JTAG
Flash
Memory
R/W
SCANSTA112
FPGA
vendor1
with JTAG
FPGA
vendor2
with JTAG
Processor
with JTAG
LSP0 LSP1 LSP2
LSP3
LSP4
SCANSTA112
SNLS161I –DECEMBER 2002–REVISED APRIL 2013 www.ti.com
Figure 1. Typical use of SCANSTA112 for board-level management of multiple scan chains.
Figure 2. Example of SCANSTA112 in a multidrop addressable backplane.
Introduction
The SCANSTA112 is the third device in a series that enable multi-drop address and multiplexing of IEEE-1149.1
scan chains. The SCANSTA112 is a superset of its predecessors - the SCANPSC110 and the SCANSTA111.
The STA112 has all features and functionality of these two previous devices.
The STA112 is essentially a support device for the IEEE 1149.1 standard. It is primarily used to partition scan
chains into managable sizes, or to isolate specific devices onto a seperate chain (Figure 1). The benefits of
multiple scan chains are improved fault isolation, faster test times, faster programiing times, and smaller vector
sets.
In addition to scan chain partitioning, the device is also addressable for use in a multidrop backplane
environment (Figure 2). In this configuration, multiple IEEE-1149.1 accessible cards with an STA112 on board
can utilize the same backplane test bus for system-level IEEE-1149.1 access. This approach facilitates a system-
wide commitment to structural test and programming throughout the entire system life sycle.
Architecture
Figure 3 shows the basic architecture of the 'STA112. The device's major functional blocks are illustrated here.
The TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and
various test data registers can be scanned to exercise the various functions of the 'STA112 (these registers
behave as defined in IEEE Std. 1149.1).
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