Datasheet

SCANSTA111
www.ti.com SNLS060K –AUGUST 2001–REVISED APRIL 2013
TESTER/SCANSTA111 INTERFACE
An IEEE 1149.1 system tester sends instructions to a 'STA111 via that 'STA111's backplane scan-port. Following
test logic reset, the 'STA111's selection state-machine is in the Wait-For-Address state. When the 'STA111's TAP
controller is sequenced to the Shift-IR state, data shifted in through the TDI
B
input is shifted into the 'STA111's
instruction register. Note that prior to successful selection of a 'STA111, data is not shifted out of the instruction
register and out through the 'STA111's TDO
B
output, as it is during normal scan operations. Instead, as each
new bit enters the instruction register's most-significant bit, data shifted out from the least-significant bit is
discarded.
When the instruction register is updated with the address data, the 'STA111's address-recognition logic
compares the seven least-significant bits of the instruction register with the 7-bit assigned address which is
statically present on the S
(0-6)
inputs. Simultaneously, the scanned-in address is compared with the reserved
Broadcast and Multi-cast addresses. If an address match is detected, the 'STA111-selection state-machine
enters one of the two selected states. If the scanned address does not match a valid single-slot address or one
of the reserved broadcast/multi-cast addresses, the 'STA111-selection state-machine enters the Unselected
state.
Note that the SLOT inputs should not be set to a value corresponding to a multi-cast group, or to the broadcast
address. Also note that the single 'STA111 selection process must be performed for all 'STA111s which are
subsequently to be addressed in multi-cast mode. This is required because each such device's Multicast Group
Register (MCGR) must be programmed with a multi-cast group number, and the MCGR is not accessible to the
test controller until that 'STA111 has first entered the Selected-Single-'STA111 state.
Once a 'STA111 has been selected, Level-2 protocol is used to issue commands and to access the chip's
various registers.
REGISTER SET
The SCANSTA111 includes a number of registers which are used for 'STA111 selection and configuration, scan
data manipulation, and scan-support operations. These registers can be grouped as shown in Table 2.
The specific fields and functions of each of these registers are detailed in the section of this document titled Data
Register Descriptions.
Note that when any of these registers is selected for insertion into the 'STA111's scan-chain, scan data enters
through that register's most-significant bit. Similarly, data that is shifted out of the register is fed to the scan input
of the next-downstream device in the scan-chain.
Table 2. REGISTER DESCRIPTIONS
Register Name BSDL Name Description
Instruction Register INSTRUCTION 'STA111 addressing and instruction-decode IEEE Std. 1149.1 required
register
Boundary-Scan Register BOUNDARY IEEE Std. 1149.1 required register
Bypass Register BYPASS IEEE Std. 1149.1 required register
Device Identification Register IDCODE IEEE Std. 1149.1 optional register
Multi-Cast Group Register MCGR 'STA111-group address assignment
Mode Register
0
MODE 'STA111 local-port configuration and control bits
Mode Register
1
N/A 'STA111 local-port configuration and control bits
(1)(2)
Mode Register
2
MODE2 'STA111 Shared GPIO configuration bits
Linear-Feedback Shift Register LFSR 'STA111 scan-data compaction (signature generation)
TCK Counter Register CNTR Local-port TCK clock-gating (for BIST)
Dedicated GPIO Register
(0-n)
N/A 'STA111 Dedicated GPIO control bits
(2)
Shared GPIO Register
(0-n)
SGPIOn 'STA111 Shared GPIO control bits
(1) One dedicated and one shared GPIO register exists for each LSP that supports dedicated and/or shared GPIO (maximum of eight
shared and eight dedicated GPIO registers).
(2) HDL version only
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