Datasheet

SCANSTA111
www.ti.com SNLS060K –AUGUST 2001–REVISED APRIL 2013
4. The TAPs are sequenced to Shift-IR and the LSB of the interrogation address is presented on the TDI
B
's.
Concurrently, the LSBs of the ones-complement slot addresses are presented on the respective TDO
B
's.
5. The weak 1 being driven on U1 and U2 is overdriven by the 0 from U3. U1 and U2 enter the Wait-For-Next-
Interrogation state.
6. The shift operation continues and U3 finishes shifting its ones-complement address (111110) out on TDO
B
.
U3 enters the Wait-For-Reset state when the TAP enters Update-IR.
7. The TAPs are again sequenced to Capture-IR and U1 and U2 shift registers latch the ones-complement
addresses (U1=101011, U2=011111).
8. The TAPs are sequenced to Shift-IR and the LSB of the interrogation address is presented on the TDI
B
's.
Concurrently, the LSBs of the ones-complement addresses are presented on the respective TDO
B
's.
9. Since both U1 and U2 are driving a weak 1 the shift continues.
10. Again U1 and U2 drive weak 1 and the shift continues.
11. U2s weak 1 is overdriven by U1s 0 and U2 enters the Wait-For-Next-Interrogation state.
12. The shift operation continues and U1 finishes shifting its ones-complement address (101011) out on TDO
B
.
U1 enters theWait-For-Reset state.
13. The instruction shift operation is repeated and U2 shifts its ones-complement address (011111) out on
TDO
B
. U2 enters the Wait-For-Reset state.
14. The instruction shift operation is repeated, however, all devices have been interrogated and are waiting for a
reset. The master device will receive all ones. This implies that there can not be an STA111 with address 0!
Figure 13. Address Interrogation State Machine
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