Datasheet

SCANSTA111
www.ti.com SNLS060K –AUGUST 2001–REVISED APRIL 2013
SVF DRIVEN, SELF-CHECKING TEST BENCH
The 'STA111 consists of 3 types of pins, dot1 backplane pins, dot1 LSP pins and support pins. The command
interpreter of the test bench is able to translate a limited set of SVF commands to the dot1 backplane pins. The
SVF shift commands contain both the stimulus (TDI
B
) and expected response (TDO
B
).
The interpreter is able to parse the following commands: ENDDR, ENDIR, RUNTEST, SDR, SIR, STATE, TRST.
PASS-THROUGH PINS
Each LSP may selectively have two pass-through pins. The pair of pass-through pins consist of an input (A
n
) and
an output (Y
n
). The LSP pass-through output (Y
n
) drives the level being received by the backplane pass-through
input (A
B
). Conversely, the level on the LSP pass-through input (A
n
) drives the backplane pass-through output
(Y
B
).
The Pass-through pins are available only when a single LSP is selected. For each LSP these pins will be
enabled when the level 2 protocol state-machine is not in the Parked-TLR state. When not enabled they are TRI-
STATED.
LSP GATING
While the LSP state-machine (level 2 protocol) is in the Parked-TLR state, the four LSP signals shall be
controlled as shown in Table 13 below. Upon entry into the Parked-TLR state (power-up, reset, PARKTLR or
GOTOWAIT) a counter in the LSP state-machine allows 512 TCK
B
clock pulses to occur on TCK
n
before gating.
Once gated, TCK
n
will drive a logic 0.
Letting 512 TCK
B
pulses pass through to TCK
n
allows a five high TMS reset to occur on over 100 levels of
hierarchy before the 'STA111 gates TCK
n
(for power saving in a free-running clock system).
Table 13. Gated LSP Drive States
LSP Connection Drive State
TDO
n
Pull-up resistor to provide a weak HIGH
TMS
n
Pull-up resistor to provide a weak HIGH
TDI
n
Pull-up resistor to provide a weak HIGH
TCK
n
TCK
B
for 512 pulses, then gated LOW
The 'STA111 does not require that any clock pulses are received on TCK
B
while in the Parked-TLR state.
Setting Bit 3 of Mode Register
0
to 1 gates TCK
n
when in the Parked-RTI, Parked-Pause-DR and Parked-Pause-
IR states. Default is free-running (bit 3 = 0). The value stored in bit 3 of Mode Register
0
does not effect the
requirement of 512 clock pulses before gating TCK
n
in the Parked-TLR state. (See section on MODE
REGISTER
0
).
IEEE 1149.4 SUPPORT
The 'STA111 provides support for a switched analog bus. Each LSP has an unparked-TLR notification pin
(LSP_ACTIVE
(0-2)
) which is low (0) when the LSP is in Parked-TLR and high (1) otherwise. This signal can be
used to enable/disable analog switches external to the 'STA111.
GPIO CONNECTIONS
General Purpose I/O (GPIO) pins are registered inputs and outputs that are parameterized in the HDL. The two
types of GPIOs than can be used in the 'STA111 are described in the next two sections. The silicon version of
the 'STA111 supports shared GPIO on all three available LSPs. The silicon version of the 'STA111 does not
support dedicated GPIO.
DEDICATED: Each LSP supports up to four (4) dedicated inputs and up to four (4) dedicated outputs. These are
separate, dedicated GPIO signals controlled by dedicated GPIO registers (one register per LSP). The GPIO
outputs are updated during the UPDATE-DR state and the GPIO input values are written to the corresponding
GPIO register during the CAPTURE-DR state. Dedicated GPIO operation is not supported in the silicon version
of the 'STA111.
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