Datasheet

SCANSTA111
SNLS060K –AUGUST 2001–REVISED APRIL 2013 www.ti.com
PARAMETERIZED DESIGN (HDL)
In order to support a large number of applications, the 'STA111 HDL is parameterized as described:
• Number of Local Scan Ports (LSPs): The 'STA111 HDL is able to simulate/synthesize a device that
contains from 1 to 8 LSPs. LSP
0
through LSP
4
are controlled via Mode Register
0
and LSP
5
through LSP
7
are
controlled via Mode Register
1
. The silicon version of the 'STA111 is synthesized with three LSPs, LSP
0
through LSP
2
.
• Number of Address Pins: The 'STA111 has a selectable number of address bits (S
0
- S
n
, where n can
range from 5 to 7). Addresses 3A through 3F hex are reserved for address interrogation, broadcast and multi-
cast addressing. The silicon version of the 'STA111 is synthesized with seven address pins.
• Pass-Through Pins: Each of the LSPs (0-n) may selectively have or not have Pass-through pins. Pass-
through pins are described in more detail below. The silicon version of the 'STA111 is synthesized with Pass-
through pins on LSP
0
and LSP
1
.
• Number/Type of GPIO bits: The 'STA111 has both dedicated and shared GPIO (General Purpose I/O).
Each dedicated group of GPIO bits supports from 0 to 4 dedicated inputs and 0 to 4 dedicated outputs. There
are provisions for specifying the default (power-up) value. TMS
(0-n)
, TDO
(0-n)
and TDI
(0-n)
are also dual purpose
pins functioning as LSP or GPIO. TMS
n
and TDO
n
are outputs, TDI
n
is an input in the GPIO mode. The
silicon version of the 'STA111 is synthesized with shared GPIO on all three available LSPs. The silicon
version of the 'STA111 does not support dedicated GPIO.
Throughout this datasheet, notations exist to clarify the differences between features available on the Silicon
version and the HDL version.
KNOWN POWER-UP STATE
The 'STA111 has a known power-up condition. This is the same state that the device is in after a TRST reset.
This happens at power-up without the presence of a TCK
B
.
Reset can also occur via a 5 TMS high reset or a SOFTRESET command.
POWER-OFF HIGH IMPEDANCE INPUTS AND OUTPUTS
The 'STA111 backplane test port features power-off high impedance inputs and outputs.
The TDI
B
, TMS
B
, and TRST
B
inputs have a 25KΩ pull-up resistor and no ESD clamp diode (ESD is controlled
with an alternate method). When the device is power-off (V
DD
floating), these inputs appear to be a capacitive
load to ground. When V
DD
= 0V (i.e.; not floating but tied to V
SS
) these inputs appear to be capacitive with the
pull-up to ground.
The TCK
B
input has no pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method).
When the device is power-off (V
DD
floating), the input appears to be a capacitive load to ground. When V
DD
= 0V
(i.e.; not floating but tied to V
SS
) the input appears to be a capacitive load to ground.
When the device is power-off (V
DD
= 0V or floating), the TDO
B
output appears to be a capacitive load.
TRST
TRST
B
: Assertion of TRST
B
will return the device back to its known power-up state.
TRST
n
: TRST
n
is an output on the LSP side of the 'STA111. While the LSP state-machine (level 2 protocol) is in
the Parked-TLR state the TRST
n
pin will be driven low. In all other states the TRST
n
pin will be driven
high.
PHYSICAL LAYER CHANGES
TRIST for TDO
B
and TDO
n
are signals for enabling an external buffer circuit between the 'STA111 and the
backplane/LSP. This would allow, for example, a CMOS-to-LVDS converter to drive an LVDS JTAG backplane
test bus. These signals are always driving. A separate TRIST is provided for each LSP to report a TRI-STATE on
TDO when the LSP is not in a shift state.
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