Datasheet

SCANSTA111
SNLS060K –AUGUST 2001–REVISED APRIL 2013 www.ti.com
BIST SUPPORT
The sequence of instructions to run BIST testing on a parked SCANSTA111 port is as follows:
1. Pre-load the Boundary register of the device under test if needed.
2. Issue the CNTRSEL instruction and initialize (load) the TCK counter to 00000000 Hex. Note that the TCK
counter is initialized to 00000000 Hex upon Test-Logic-Reset, so this step may not be necessary.
3. Issue the CNTRON instruction to the 'STA111, to enable the TCK counter.
4. Shift the PARKRTI instruction into the 'STA111 instruction register and BIST instruction into the instruction
register of the device under test. With the counter on (at terminal count) and the LSP parked, the local TCK
is gated.
5. Issue the CNTRSEL instruction to the 'STA111.
6. Load the TCK counter (Shift the 32-bit value representing the number of TCK
n
cycles needed to execute the
BIST operation into the TCK counter register). The Self test will begin on the rising edge of TCK
B
following
the Update-DR TAP controller state.
7. Bit 7 of Mode Register
0
can be scanned to check the status of the TCK counter, (MODESEL instruction
followed by a Shift-DR). Bit 7 logic 0 means the counter has not reached terminal count, logic 1 means that
the counter has reached terminal count and the BIST operation has completed.
8. Execute the CNTROFF instruction.
9. Unpark the LSP and scan out the result of the BIST operation
RESET
Reset operations can be performed at three levels. The highest level resets all 'STA111 registers and all of the
local scan chains of selected and unselected 'STA111s. This Level 1 reset is performed whenever the 'STA111
TAP Controller enters the Test-Logic-Reset state. Test-Logic-Reset can be entered synchronously by forcing
TMS
B
high for at least five (5) TCK
B
pulses, or asynchronously by asserting the TRST
B
pin. A Level 1 reset
forces all 'STA111s into the Wait-For-Address state, parks all local scan chains in the Test-Logic-Reset state,
and initializes all 'STA111 registers.
The SOFTRESET instruction is provided to perform a Level 2 reset of all LSP's of selected 'STA111s.
SOFTRESET forces all TMS
n
signals high, placing the corresponding local TAP Controllers in the Test-Logic-
Reset state within five (5) TCK
B
cycles.
The third level of reset is the resetting of individual local ports. An individual LSP can be reset by parking the port
in the Test-Logic-Reset state via the PARKTLR instruction. To reset an individual LSP that is parked in one of
the other parked states, the LSP must first be unparked via the UNPARK instruction.
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of the four TAP Controller states: Test-Logic-Reset, Run-
Test/Idle, Pause-DR, or Pause-IR. The 'STA111 is able to park a local chain by controlling the local Test Mode
Select outputs (TMS
(0-2)
) (see Figure 4). TMS
n
is forced high for parking in the Test-Logic-Reset state, and forced
low for parking in Run-Test/Idle, Pause-IR, or Pause-DR states. Local chain access is achieved by issuing the
UNPARK instruction. The LSPs do not become unparked until the 'STA111 TAP Controller is sequenced through
a specified synchronization state. Synchronization occurs in the Run-Test/Idle state for LSPs parked in Test-
Logic-Reset or Run-Test/Idle; and in the Pause-DR or Pause-IR state for ports parked in Pause-DR or Pause-IR,
respectively.
Figure 11 and Figure 12 show the waveforms for synchronization of a local chain that was parked in the Test-
Logic-Reset state. Once the UNPARK instruction is received in the instruction register, the LSPC forces TMS
n
low on the falling edge of TCK
B
.
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