Datasheet

SCANSTA111
SNLS060K –AUGUST 2001–REVISED APRIL 2013 www.ti.com
Bit 3 is normally set to logic 0 so that TCK
n
is free-running when the local scan ports are parked in the Parked-
RTI, Parked-Pause-DR or Parked-Pause-IR state. When the local ports are parked, bit 3 can be programmed
with logic 1, forcing all of the LSP TCK
n
's to stop. This feature can be used in power sensitive applications to
reduce the power consumed by the test circuitry in parts of the system that are not under test. When in the
Parked-TLR state, TCK
n
is gated (stopped) after 512 clock pulses have been received on TCK
B
independent of
the bit 3 value.
Bit 7 is a status bit for the TCK counter. Bit 7 is only set (logic 1) when the TCK counter is on and has reached
terminal count (zero). It is cleared (logic 0) when the counter is loaded following a CNTRSEL instruction. The
power-on value for bit 7 is 0.
Bits 5 and 6 are optional in the HDL to support five LSPs with a single Mode Register
0
. A second Mode
Register
1
may be added to allow support of up to eight LSPs.
Table 8. Mode Register
0
BIT 7 6 5 4 3 2 1 0
Description TCK Counter LSP
4
LSP
3
TDI
B
to TDO
B
TCK Free LSP
2
LSP
1
LSP
0
Status Loopback Running
Disable
Used in Y N N Y Y Y Y Y
Silicon
Default Value 0 0 0 0 0 0 0 1
Table 9. Mode Register
1
BIT 7 6 5 4 3 2 1 0
Description Reserved Reserved Reserved Reserved Reserved LSP
7
LSP
6
LSP
5
Used in N N N N N N N N
Silicon
Default Value 0 0 0 0 0 0 0 0
Table 10. Mode Register
2
BIT 7 6 5 4 3 2 1 0
Description LSP
7
/GPIO
7
LSP
6
/GPIO
6
LSP
5
/GPIO
5
LSP
4
/GPIO
4
LSP
3
/GPIO
3
LSP
2
/GPIO
2
LSP
1
/GPIO
1
LSP
0
/GPIO
0
Used in N N N N N Y Y Y
Silicon
Default Value 0 0 0 0 0 0 0 0
DEVICE IDENTIFICATION REGISTER
The device identification register (IDREG) is a 32-bit register compliant with IEEE Std. 1149.1. When the
IDCODE instruction is active, the identification register is loaded with the Hex value upon leaving the Capture-DR
state (on the rising edge of the TCK
B
). Refer to the currently available BSDL file on our website for the most
accurate Device ID.
LINEAR FEEDBACK SHIFT REGISTER
The 'STA111 contains a signature compactor which supports test result evaluation in a multi-chain environment.
The signature compactor consists of a 16-bit linear-feedback shift register (LFSR) which can monitor local-port
scan data as it is shifted upstream from the 'STA111's local-port network. Once the LFSR is enabled, the LFSR's
state changes in a reproducible way as each local-port data bit is shifted in from the local-port network. When all
local-port data has been scanned in, the LFSR contains a 16-bit signature value which can be compared against
a signature computed for the expected results vector.
The LFSR uses the following feedback polynomial:
F(x) = X
16
+ X
12
+ X
3
+ X + 1 (1)
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