Datasheet
SCANSTA111
www.ti.com
SNLS060K –AUGUST 2001–REVISED APRIL 2013
MODE REGISTER
0
Mode Register
0
is an 8-bit data register used primarily to configure the Local Scan Port Network. Mode Register
0
is initialized to 00000001 binary upon entering the Test-Logic-Reset state. Bits 0, 1, 2, and 4 are used for scan
chain configuration as described in Table 6. When the UNPARK instruction is executed, the scan chain
configuration is as shown in Table 6 below. When all LSPs are parked, the scan chain configuration is TDI
B
→
'STA111-register → TDO
B
. Bit 3 is used for TCK
n
configuration, see Table 7.
Table 6. Mode Register Control of LSPN
(1)
Mode Register(s) Scan Chain Configuration (if unparked)
MR0: X000X000 TDI
B
→ Register → TDO
B
MR0: X000X001 TDI
B
→ Register → LSP
0
→ PAD → TDO
B
MR0: X000X010 TDI
B
→ Register → LSP
1
→ PAD → TDO
B
MR0: X000X011 TDI
B
→ Register → LSP
0
→ PAD → LSP
1
→ PAD → TDO
B
MR0: X000X100 TDI
B
→ Register → LSP
2
→ PAD → TDO
B
MR0: X000X101 TDI
B
→ Register → LSP
0
→ PAD → LSP
2
→ PAD → TDO
B
MR0: X000X110 TDI
B
→ Register → LSP
1
→ PAD → LSP
2
→ PAD → TDO
B
MR0: X000X111 TDI
B
→ Register → LSP
0
→ PAD → LSP
1
→ PAD → LSP
2
→ PAD → TDO
B
MR0: X010X000 TDI
B
→ Register → LSP
3
→ PAD → TDO
B
MR0: X010X001 TDI
B
→ Register → LSP
0
→ PAD → LSP
3
→ PAD → TDO
B
MR0: X010X010 TDI
B
→ Register → LSP
1
→ PAD → LSP
3
→ PAD → TDO
B
MR0: X010X011 TDI
B
→ Register → LSP
0
→ PAD → LSP
1
→ PAD → LSP
5
→ PAD → TDO
B
MR0: X010X100 TDI
B
→ Register → LSP
2
→ PAD → LSP
3
→ PAD → TDO
B
... ...
MR0: X110X111 TDI
B
→ Register → LSP
0
→ PAD → LSP
1
→ PAD → LSP
2
→ PAD → LSP
3
→ PAD → LSP
4
→ PAD → TDO
B
MR0: X000X000MR1: TDI
B
→ Register → LSP
5
→ PAD → TDO
B
XXXXX001
(2)
MR0: X000X001MR1: TDI
B
→ Register → LSP
0
→ PAD → LSP
5
→ PAD → TDO
B
XXXXX001
(2)
MR0: X000X010MR1: TDI
B
→ Register → LSP
1
→ PAD → LSP
5
→ PAD → TDO
B
XXXXX001
(2)
... ...
MR0: X110X111MR1: TDI
B
→ Register → LSP
0
→ PAD →→ LSP
1
→ PAD → LSP
2
→ PAD → LSP
3
→ PAD → LSP
4
→ PAD → LSP
5
→
XXXXX001
(2)
PAD → TDO
B
MR0: X000X000MR1: TDI
B
→ Register → LSP
6
→ PAD → TDO
B
XXXXX010
(2)
... ...
MR0: X110X111MR1: TDI
B
→ Register → LSP
0
→ PAD → LSP
1
→ PAD → LSP
2
→ PAD → LSP
3
→ PAD → LSP
4
→ PAD → LSP
5
→
XXXXX111
(2)
PAD → LSP
6
→ PAD → LSP
7
→ PAD → TDO
B
MR0: TDI
B
→ Register → TDO
B
(Loopback)
XXX1XXXXMR1:
XXXXXXXX
(2)
(1) In a device with 8 LSPs there are 2
8
possible LSPN configurations: No LSPs, each individual LSP, combinations of 2 to 7 LSPs, and all
8 LSPs.
(2) Mode Register
1
is only available in the HDL version (up to eight LSPs). The Silicon version has three LSPs and uses Mode Register
0
for
LSP selection.
Table 7. Test Clock Configuration
Bit 3 LSP n TCK n
1 Parked Stopped
0 Parked Free-running
1 Unparked Free-running
0 Unparked Free-running
X Parked-TLR Stopped after 512 clock pulses
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