Datasheet
SCANSTA111
SNLS060K –AUGUST 2001–REVISED APRIL 2013
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REGISTER DESCRIPTIONS
INSTRUCTION REGISTER
The instruction shift register is an 8-bit register that is in series with the scan chain whenever the TAP Controller
of the SCANSTA111 is in the Shift-IR state. Upon exiting the Capture-IR state, the value XXXXXX01 is captured
into the instruction register, where XXXXXX represents the value on the S
(0-6)
inputs. When the 'STA111
controller is in the Wait-For-Address state, the instruction register is used for 'STA111 selection via address
matching. In addressing individual 'STA111s, the chip's addressing logic performs a comparison between a
statically-configured (hard-wired) value on that 'STA111's slot inputs, and an address which is scanned into the
chip's instruction register. Binary address codes 000000 through 111010 (00 through 3A Hex) are reserved for
addressing individual 'STA111s. Address 3B Hex is for Broadcast mode.
During multi-cast (group) addressing, a scanned-in address is compared against the (previously scanned-in)
contents of a 'STA111's Multi-Cast Group register. Binary address codes 111110 through 111111 (3A through 3F
Hex) are reserved for multi-cast addressing, and should not be assigned as 'STA111 slot-input values.
BOUNDARY-SCAN REGISTER
The boundary-scan register is a sample only shift register containing cells from the S
(0-6)
and OE inputs. The
register allows testing of circuitry external to the 'STA111. It permits the signals flowing between the system pins
to be sampled and examined without interfering with the operation of the on-chip system logic.
The scan chain is arranged as follows:
TDI
B
→ OE→ S
6
→ S
5
→ S
4
→ S
3
→ S
2
→ S
1
→ S
0
→ TDO
B
BYPASS REGISTER
The bypass register is a 1-bit register that operates as specified in IEEE Std. 1149.1 once the 'STA111 has been
selected. The register provides a minimum length serial path for the movement of test data between TDI
B
and
the LSPN. This path can be selected when no other test data register needs to be accessed during a board-level
test operation. Use of the bypass register shortens the serial access-path to test data registers located in other
components on a board-level test data path.
MULTI-CAST GROUP REGISTER
Multi-cast is a method of simultaneously communicating with more than one selected 'STA111. The multi-cast
group register (MCGR) is a 2-bit register used to determine which multi-cast group a particular 'STA111 is
assigned to. Four addresses are reserved for multi-cast addressing. When a 'STA111 is in the Wait-For-Address
state and receives a multi-cast address, and if that 'STA111's MCGR contains a matching value for that multi-
cast address, the 'STA111 becomes selected and is ready to receive Level 2 Protocol (i.e., further instructions).
The MCGR is initialized to 00 upon entering the Test-Logic-Reset state.
Table 5. Multi-Cast Group Register Addressing
MCGR Bits 1,0 Hex Address Binary Address
00 3C 00111100
01 3D 00111101
10 3E 00111110
11 3F 00111111
The following actions are used to perform multi-cast addressing:
1. Assign all target 'STA111s to a multi-cast group by writing each individual target 'STA111's MCGR with the
same multi-cast group code (see Table 5). This configuration step must be done by individually addressing
each target 'STA111, using that chip's assigned slot value.
2. Scan out the multi-cast group address through the TDI
B
input of all 'STA111s. Note that this occurs in
parallel, resulting in the selection of only those 'STA111s whose MCGR was previously programmed with the
matching multi-cast group code.
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