Datasheet

SCANSTA101
www.ti.com SNLS057J –MAY 2002–REVISED APRIL 2013
AC ELECTRICAL CHARACTERISTICS/OPERATING REQUIREMENTS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified. C
L
= 50 pF, R
L
= 500Ω
unless otherwise specified.
Symbol Parameter Conditions # of SCK Min Max Units
(1)(2)
t
D3
Propagation Delay
Output data valid to DTACK low, all read See Figure 13 1 ns
cycles
t
pHL1
Propagation Delay 10.5
STB low to INT low, register write (clears See Figure 12 5 or 6 ns
Interrupt)
t
W
Clock Pulse Width, SCK, H or L 3.0 ns
f
MAX
Clock Frequency, SCK 66 MHz
t
RELEASE
Release Time, RST to STB 2 ns
Symbol Parameter Conditions Min Max Units
SERIAL SCAN INTERFACE (SSI)
t
D5
Propagation Delay
See Figure 14 11.5 ns
SCK to TCK_SM
t
D6
Propagation Delay
See Figure 14 12.0 ns
SCK to TDO_SM
t
D7
Propagation Delay
See Figure 14 12.5 ns
SCK to TMS_SM
t
D8
Propagation Delay - tpLH
See Figure 14 15.0 ns
SCK to TRIST_SM
t
D9
Propagation Delay - tpHL
See Figure 14 12.5 ns
SCK to TRIST_SM
t
D10
Propagation Delay
See Figure 14 12.5 ns
SCK to TDO_SM disable
t
D11
Propagation Delay See Figure 14 14.0 ns
SCK to TDO_SM enable
t
EN1
Enable Delay See Figure 14 12.0 ns
OE low to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
t
DIS1
Disable Delay See Figure 14 11.0 ns
OE high to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
t
EN2
Enable Delay 10.0 ns
OE low to TRIST_SM
t
DIS2
Disable Delay 11.5 ns
OE high to TRIST_SM
t
DIS3
Disable Delay 12.5 ns
RST low to TRST0_SM
t
S2
Setup Time See Figure 14 3.5 ns
SCK to TDI_SM
t
H2
Hold Time See Figure 14 2.0 ns
SCK to TDI_SM
TEST & DEBUG INTERFACE TIMING REQUIREMENTS (SCAN)
t
S
Setup Time 2.0 ns
TMS to TCK
t
H
Hold Time 1.0 ns
TMS to TCK
t
S
Setup Time 1.0 ns
TDI to TCK
t
H
Hold Time 2.0 ns
TDI to TCK
t
W
Pulse Width 10.0 ns
TCK (H or L)
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