Datasheet

SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013 www.ti.com
Table 36. Boundary Scan Register Definition
BSR Signal Name BSR Signal Name BSR Signal Name BSR Signal Name
Bit# Bit# Bit# Bit#
0 SCK 10 DTACK 20 DATA[7] 30 TCK_SM
1 RST 11 INT 21 DATA[6] 31 TRST0_SM
2 R/W 12 DATA[15] 22 DATA[5] 32 TDI_SM
3 STB 13 DATA[14] 23 DATA[4] 33 OE
4 CE 14 DATA[13] 24 DATA[3] 34 TRIST
5 ADDRESS[4] 15 DATA[12] 25 DATA[2]
6 ADDRESS[3] 16 DATA[11] 26 DATA[1]
7 ADDRESS[2] 17 DATA[10] 27 DATA[0]
8 ADDRESS[1] 18 DATA[9] 28 TDO_SM
9 ADDRESS[0] 19 DATA[8] 29 TMS_SM
BIST SUPPORT
The memory BIST can be initiated through JTAG interface using the RUNBIST instruction or by setting the
Onboard Memory BIST bit in the Start register. When the memory BIST is initiated through the JTAG interface
the result of pass/fail will be set in the Memory BIST Result bit in the Status register and also in the BIST status
register that can be accessed through the JTAG interface. The BIST status register is a one bit register and is
connected in the serial path of TDO and TDI when the RUNBIST instruction is scanned into the instruction
register. Once the BIST is done, the contents of the BIST status register can be scanned out to determine
whether the memory BIST passed or failed. If the memory BIST is initiated through the Onboard Memory BIST
bit in the Start register the result of pass/fail will be set only in the BIST Result bit in the status register. The
memory BIST will initialize the memory to zero.
32 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated
Product Folder Links: SCANSTA101