Datasheet

SCANSTA101

www.ti.com

SNLS057J –MAY 2002–REVISED APRIL 2013

RESET STRATEGY

The incoming external hardware reset (RST) will be synchronized to the incoming clock (SCK) and is combined

with the soft reset to generate a synchronized internal reset (SYS_RST_N). During operation, the chip can be

reset by writing a '1' to the Reset bit in the Setup register. All logic throughout the device will be initialized, all

control and status registers will be in a known default state, all PPI memory address pointers will default to their

respective base addresses, the SSI memory pointer will default to zero, the Tap Tracker will be reset to TLR, and

the clock division counter will be initialized to all zeroes after deassertion of the internal reset. The Reset bit in

the Setup register is self clearing. The TRST bit in the Setup register, when set, resets the SSI logic and drives

the TRST0_SM and TRST1_SM to zero.

SOFTWARE INTERFACE DETAILS

The following sections include descriptions of each addressable register in the ScanMaster memory space.

Following the title of the particular register, the mnemonic for the register is included in parentheses as well as

the physical address location in hexadecimal notation (value preceded by $). KEY- RO: Read Only; RW:

Read/Write.

Table 17. Start Register (START) ($00)

Bit(s) Type Field Address Offset Reset Value Reset Source

15:14 RO Reserved 0 00b

13 RW Onboard Memory BIST 0 0b SYS_RST

12:9 RO Reserved 0 0000b

8 RW Use Sequencer 0 0b SYS_RST

7:3 RO Reserved Use Vector x

(1)

0 0000h

2:0 RW Use Vector x 0 000b SYS_RST

(1) Reserved Use Vector x for future growth for the number of vectors.

Onboard Memory BIST ScanMaster memory BIST enable. This bit is self clearing when BIST result is written to the Memory

BIST Result bit in the Status register.

'1' Initiate on chip memory BIST

'0' On chip memory BIST complete

Use Sequencer Sequencer enable/disable (For preloaded vectors only)

'1' Enable sequencer

'0' Disable sequencer

Use Vector <2:0> Use Vector x designates the vector "x" which is enabled, where "x" is the vector number, a binary

encoding of bits <2:0>. Only vectors 1 through 4 are valid. Vectors 5 through 7 reserved for future

use.

'000' No vector enabled

'001' Vector 1 enabled

'010' Vector 2 enabled

'011' Vector 3 enabled

'100' Vector 4 enabled

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