Datasheet

SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013 www.ti.com
HARDWARE INTERFACE DETAILS
Table 13. System Interface Signal Description
Signal Name No. of Pin Type Driver Type Freq. MHz Description
Bits
SCK 1 I LVTTL 66 System Clock: This is the main clock signal to the SCANSTA101.
SCK is used to clock all internal circuitry
RST 1 I,H LVTTL N/A Hardware Reset signal (with hysteresis (H)): This is the
SCANSTA101 asynchronous reset signal. This signal resets the
entire SCANSTA101 and sets all registers to their respective
default values.
OE 1 I LVTTL N/A Output enable: will TRI-STATE all 1149.1 outputs when high.
Table 14. Parallel Processor Interface Signal Descriptions
Signal Name No. of Pin Type Driver Type Freq. MHz Description
Bits
DATA(31:16) 16 I/O LVTTL (weakest N/A Bidirectional Data Bus. Not bonded out in packaged part. These
driver) are only used in the 32-bit macro version.
DATA(15:0) 16 I/O LVTTL N/A Bidirectional Data Bus.
ADDRESS(4:0) 5 I LVTTL N/A Address Bus
CE 1 I LVTTL N/A Chip Enable, when low, enables the PPI for transfers.
DATA(31:0) and DTACK are tristated when CE is high.
R/W 1 I LVTTL N/A Read/Write defines a PPI cycle. Read when high, write when low.
STB 1 I LVTTL N/A Strobe is used for timing all PPI transfers. DATA(31:0) are
tristated when STB is high. Data valid setup is with respect to the
falling edge of STB and data valid hold is with respect to rising
edge of STB.
DTACK 1 O O/D N/A Data Acknowledge (open drain - sustained tristate). DTACK is
used to synchronize asynchronous transfers between the host
and the SCANSTA101. During write cycles, DTACK goes low
when data has been registered and then goes to high impedance
when the cycle has been completed. During read cycles DTACK
goes low when data bus is driven with the valid data and then
goes to high impedance when the cycle has been completed.
INT 1 O LVTTL N/A Interrupt is used to trigger a host interrupt for any of the defined
interrupt events. Signal is active high.
Table 15. Serial Scan Interface Signal Descriptions
Signal Name No. Pin Type Driver Type Freq. MHz Description
TDI_SM 1 I LVTTL up to 25 ScanMaster Test Data Input (weak pullup)
TDO_SM 1 O LVTTL up to 25 ScanMaster Test Data Output
TMS_SM 1 O LVTTL up to 25 ScanMaster Test Mode Select
TCK_SM 1 O LVTTL up to 25 ScanMaster Test Clock
TRST0_SM 1 O LVTTL N/A ScanMaster Test Reset
TRST1_SM 1 O LVTTL N/A Redundant ScanMaster Test Reset (not bonded out)
TRIST_SM 1 O LVTTL N/A The tristate notification pin exerts a high when TDO_SM is
tristated.
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