Datasheet

SCANSTA101
SNLS057J –MAY 2002–REVISED APRIL 2013 www.ti.com
SERIAL SCAN INTERFACE CONTROLLER AND SCANBRIDGE CONTROLLER
The Serial Scan Interface Controller (SSIC) remains in the Idle state until new data are written to the Start
register. When this event occurs the following operations are performed:
1. If the ScanBridge Support Initiate/Release bit was not set previously and is currently set in the Setup
register, the SSIC initializes the ScanBridge Controller (SBC) to perform the following steps to set up all
ScanBridges in the hierarchy.
(a) Determine the number of levels of ScanBridge support to be inserted (from the ScanBridge support
structure)
(b) Sequence TMS_SM so that all ScanBridges in the same level of hierarchy enter the SIR state, and then
shift in the address (from the ScanBridge structure) to select a ScanBridge in the current level of
hierarchy. The ScanBridge's TAP controller is then sequenced through the Update-IR state.
(c) Sequence TMS_SM so that the selected ScanBridge's TAP controller enters the SIR state, then scan in
the MODESEL instruction to put its mode register in the data path.
(d) Sequence the selected ScanBridge's TAP controller to enter the Shift-DR state and scan in the LSP
contents (from the ScanBridge structure) into its mode register. The ScanBridge's TAP controller is then
sequenced through the Update-DR state.
(e) Repeat Step 1C, but this time scan in the UNPARK instruction so that the LSP is inserted into the active
scan chain.
(f) Sequence the ScanBridge's TAP controller to enter the RTI state (the LSP will not be unparked until its
TAP controller enters RTI).
(g) Repeat Steps 1B through Step 1G to configure the ScanBridges in the remaining hierarchy levels. One
set of pre-shift pad and post-shift pad bits is added to the patterns for each hierarchy level between the
STA Master and the ScanBridge being configured. The pad bits are used to bypass the intermediate
levels of hierarchy.
(h) For the subsequent vectors, if the TAP Tracker enters the
(a) SDR state, the SCANSTA101 will add one pre-shift bit for the pad register and one post-shift bit for
the bypass register for each level of hierarchy.
(b) SIR state, the SCANSTA101 will add one pre-shift bit for the pad register and eight post-shift bits for
the ScanBridge instruction register for each level of hierarchy. The eight post-shift bits will be all
ones, forcing the ScanBridge into bypass mode.
(i) The pad bits need to be stripped when loading a vector into TDI_SM. This will be done by having a
status flag to indicate whether the vector that is being scanned out has ScanBridge support or not. If the
scanned-out vector has ScanBridge support, then the pad bits will be stripped when the TAP Tracker
enters the SDR or SIR states.
2. If the ScanBridge Support Initiate/Release bit was set previously and is currently reset in the Setup register,
the SSIC will toggle TCK_SM five times while TMS_SM is held high. This will return all selected ScanBridges
to the wait-for-address state and park the LSPs in the Test-Logic-Reset state. When the ScanBridge support
is released the user should make sure that the Use Vector and Use Sequencer bits in the Start register are
not set, so that the SSIC will not start processing a vector or the sequencer immediately after releasing the
ScanBridge support. Once the ScanBridge support is released the user may start processing a vector or the
sequencer by writing to the Start register.
3. If the sequencer is enabled (the Use Sequencer bit in the Start register is one),
(a) Clear the Results of Compare bit and set the Using Sequencer bit in the Status register.
(b) Fetch the sequence repeat count.
(c) If the sequence repeat count is zero, the sequence is complete so reset the Using Sequencer bit and
return to the Idle state, otherwise fetch the next vector number and its repeat count.
(d) If the vector number is zero, decrement the sequence repeat count and return to Step 3C. If the vector
number is illegal, i.e., other than 001, 010, 011, or 100, decrement the sequence repeat count and return
to Step 3C.
(e) If the vector repeat count is equal to zero, fetch the next vector number and its repeat count and go to
Step 3D. If the repeat count is non-zero fetch the vector structure.
(f) If the pre-load bit in the vector structure is not set, reset the Using Sequencer bit and return to the Idle
state.
4. If the sequencer is not enabled but a vector is enabled (the Use Vector bits in the Start register are non-
zero), fetch the current vector structure and set the appropriate Using Vector bits in the Status register. If
neither the sequencer nor a vector is enabled, return to the Idle state.
5. Fetch the Macro Structure to be used, set the vector/macro control bits and store the TMS_SM bits in the
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