Datasheet

SCANSTA101

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SNLS057J –MAY 2002–REVISED APRIL 2013

COMPARATOR AND EXPECTED/MASK REGISTERS

The One-Bit Comparator, when enabled, compares the TDI_SM input with expected data. When the compare

feature is enabled (in preloaded vector mode only) the SSIC pre-fetches data into Expected and Mask registers

from the address locations for the current vector being processed. The comparator will compare each bit on the

TDI_SM input with the corresponding bit from the expected register. If the mask feature is enabled, then the

comparison is performed only on those bits that are not masked, i.e., on those bits for which the mask is set to

zero. Table 11 shows how the Compare and Use Mask/Compare bits in the Macro Structure are used.

Table 11. Compare and Use Mask/Compare Bit Descriptions

Compare Use Mask/Compare Description

0 0 Do Not Compare

0 1 Compare with Mask

1 0 Compare without Mask

1 1 Compare with Mask

The Results of Compare bit (bit 15 of Status register) stores the comparison results in the status register. This bit

defaults to fail (zero) and will be updated only after the current vector is processed. In the case of a single vector

the Results of Compare bit will be set to one (pass) only if all the bits in the scanned in vector match the

expected vector. However, in the case of the sequencer only the results of final vector comparison will be taken

into account.

Each vector within the sequencer is repeated until the vector repeat count is exhausted. The sequence is

repeated until the sequencer repeat count is exhausted.

Figure 7 illustrates the compare logic.

After reset and before every sequencer process, flip-flops 1 and 3 are initialized to zero while flip-flop 2 is set to

1. When the compare feature is enabled flip-flop 1 is continuously updated with the immediate comparison

results (1 for pass and 0 for fail). Flip-flop 2 is reset to zero when a mismatch occurs and remains in this state for

the remainder of the current vector processing. When the current vector is completely processed flip-flop 3

(Results of Compare register) will be updated with the current status.

Figure 7. Compare Logic

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