Datasheet

SCAN921025H, SCAN921226H
www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
RFCP
REFCLK Period 12.5 T 50.0 ns
t
RFDC
REFCLK Duty Cycle 30 50 70 %
t
RFCP
/
Ratio of REFCLK to TCLK 95 1 105
t
TCP
t
RFTT
REFCLK Transition Time 3 6 ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
Receiver out Clock t
RCP
= t
TCP
RCLK 12.5 50.0 ns
Period Figure 12
t
CLH
CMOS/TTL Low-to-High
1.2 4 ns
Rout(0-9),
Transition Time
CL = 15 pF
LOCK,
Figure 6
t
CHL
CMOS/TTL High-to-Low
RCLK
1.1 4 ns
Transition Time
t
DD
All Temp, All Freq 1.75*t
RCP
+1.25 1.75*t
RCP
+5.0 1.75*t
RCP
+8.5 ns
Deserializer Delay
Room Temp, 3.3V 20MHz 1.75*t
RCP
+2.25 1.75*t
RCP
+5.0 1.75*t
RCP
+8.0 ns
Figure 13
Room Temp, 3.3V 80MHz 1.75*t
RCP
+2.25 1.75*t
RCP
+5.0 1.75*t
RCP
+8.0 ns
t
ROS
RCLK
0.4*t
RCP
0.5*t
RCP
ns
20MHz
ROUT Data Valid before
Figure 14
RCLK
RCLK
0.35*t
RCP
0.5*t
RCP
ns
80MHz
t
ROH
20MHz -0.4*t
RCP
-0.5*t
RCP
ns
ROUT Data Valid after
Figure 14
RCLK
80MHz -0.35*t
RCP
-0.5*t
RCP
ns
t
RDC
RCLK Duty Cycle 45 50 55 %
t
HZR
HIGH to Tri-state Delay 2.8 10 ns
t
LZR
LOW to Tri-state Delay 2.8 10 ns
Figure 15 Rout(0-9)
t
ZHR
Tri-state to HIGH Delay 4.2 10 ns
t
ZLR
Tri-state to LOW Delay 4.2 10 ns
t
DSR1
Deserializer PLL Lock 20MHz 1.7 3.5 μs
Time from PWRDWN
80MHz 1.0 2.5 μs
(with SYNCPAT)
Figure 16
t
DSR2
20MHz 0.65 1.5 μs
Deserializer PLL Lock
Figure 17
(1)
time from SYNCPAT
80MHz 0.29 0.8 μs
t
ZHLK
Tri-state to HIGH Delay
LOCK 3.7 12 ns
(power-up)
t
RNMI-R
VCC = 3.15 to 3.6V +335
80MHz ps
Ideal Noise Margin Right
VCC = 3.0V +215
Figure 21
20MHz +1 ns
t
RNMI-L
VCC = 3.15 to 3.6V -395
80MHz ps
Ideal Noise Margin Left
VCC = 3.0V -520
Figure 21
20MHz -1 ns
(1) For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and
with specific conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either
t
DSR1
timing or t
DSR2
timing. t
DSR1
is the time required for the deserializer to indicate lock upon power-up or when leaving the power-
down mode. Synchronization patterns should be sent to the device before initiating either condition. t
DSR2
is the time required to indicate
lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs).
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