Datasheet
SCAN921025H, SCAN921226H
SNLS185C –OCTOBER 2004–REVISED MAY 2013
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
I
ILR
V
CC
= 3.6V, V
IN
= 0V, pins TMS, TDI, and
Input Current -20 -10 μA
TRST
V
OH
High Level Output Voltage V
CC
= 3.0V, I
OH
= −12 mA, TDO output 2.2 2.6 V
V
OL
Low Level Output Voltage V
CC
= 3.0V, I
OL
= 12 mA, TDO output 0.3 0.5 V
I
OS
Output Short Circuit Current V
CC
= 3.6V, V
OUT
= 0.0V, TDO output -15 -90 -120 mA
I
OZ
Tri-state Output Current PWRDN or REN = 0.8V, V
OUT
= 0V or VCC −10 0 +10 μA
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
Transmit Clock Period 12.5 T 50.0 ns
t
TCIH
Transmit Clock High Time 0.4T 0.5T 0.6T ns
t
TCIL
Transmit Clock Low Time 0.4T 0.5T 0.6T ns
t
CLKT
TCLK Input Transition Time 3 6 ns
t
JIT
ps
TCLK Input Jitter 150
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
LLHT
Bus LVDS Low-to-High
0.2 0.4 ns
R
L
= 27Ω
Transition Time
C
L
=10pF to GND
t
LHLT
Bus LVDS High-to-Low
Figure 5
(1)
0.25 0.4 ns
Transition Time
t
DIS
DIN (0-9) Setup to TCLK R
L
= 27Ω, 0 ns
C
L
=10pF to GND
t
DIH
DIN (0-9) Hold from TCLK 4.0 ns
Figure 8
t
HZD
DO ± HIGH to
3 10 ns
Tri-state Delay
t
LZD
DO ± LOW to Tri-state
3 10 ns
R
L
= 27Ω,
Delay
C
L
=10pF to GND
t
ZHD
DO ± Tri-state to HIGH
Figure 9
(2)
5 10 ns
Delay
t
ZLD
DO ± Tri-state to LOW
6.5 10 ns
Delay
t
SPW
SYNC Pulse Width 5*t
TCP
ns
R
L
= 27Ω
Figure 11
t
PLD
Serializer PLL Lock Time 510*t
TCP
513*t
TCP
ns
t
SD
Serializer Delay R
L
= 27Ω, Figure 12 t
TCP
+ 1.0 t
TCP
+ 2.5 t
TCP
+ 3.5 ns
t
DJIT
20MHz -330 140 ps
R
L
= 27Ω,
Deterministic Jitter
C
L
=10pF -130 -40 +60 ps
80MHz
to GND
(3)
t
RJIT
Random Jitter 6 10 ps (RMS)
(1) t
LLHT
and t
LHLT
specifications are Guaranteed By Design (GBD) using statistical analysis.
(2) Because the Serializer is in tri-state mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(3) t
DJIT
specifications are Guaranteed By Design using statistical analysis.
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