Datasheet

SCAN921025H, SCAN921226H
www.ti.com SNLS185C –OCTOBER 2004–REVISED MAY 2013
Tri-state
The Serializer enters tri-state when the DEN pin is driven low. This puts both driver output pins (DO+ and DO−)
into tri-state. When you drive DEN high, the Serializer returns to the previous state, as long as all other control
pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
When you drive the REN pin low, the Deserializer enters tri-state. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK will enter tri-state. The LOCK output remains active, reflecting the state of the PLL.
Table 1.
Random Lock Times for the SCAN921226H
(1)
80 MHz Units
Maximum 18 μs
Mean 3.0 μs
Minimum 0.43 μs
Conditions: PRBS 2
15
, V
CC
= 3.3V
(1) Difference in lock times are due to different starting points in the data pattern with multiple parts.
Test Modes
In addition to the IEEE 1149.1 test access to the digital TTL pins, the SCAN921025H and SCAN921226H have
two instructions to test the LVDS interconnects. The first is EXTEST. This is implemented at LVDS levels and is
only intended as a go no-go test (e.g. missing cables). The second method is the RUNBIST instruction. It is an
"at-system-speed" interconnect test. It is executed in approximately 28mS with a system clock speed of 80MHz.
There are two bits in the RX BIST data register for notification of PASS/FAIL and TEST_COMPLETE. Pass
indicates that the BER (Bit-Error-Rate) is better than 10
-7
.
An important detail is that once both devices have the RUNBIST instruction loaded into their respective
instruction registers, both devices must move into the RTI state within 4K system clocks (At a SCLK of 66Mhz
and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the same scan
chain or LSP, however, it can be a problem with some multi-drop devices. This test mode has been simulated
and verified using TI's SCANSTA111.
DIN0 Held Low-DIN1 Held High Creates an RMT Pattern
DIN4 Held Low-DIN5 Held High Creates an RMT Pattern
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