Datasheet

SCAN921025H, SCAN921226H
SNLS185C –OCTOBER 2004–REVISED MAY 2013 www.ti.com
Deserializer Pin Descriptions
Pin Name I/O Ball Id. Description
ROUT O A5, B4, B6, C4, Data Output. ±9 mA CMOS level outputs.
C7, D6, F5, F7,
G4, G5
RCLKR/F I B3 Recovered Clock Rising/Falling strobe select. TTL level input. Selects
RCLK active edge for strobing of ROUT data. High selects rising edge. Low
selects falling edge.
RI+ I D2 + Serial Data Input. Non-inverting Bus LVDS differential input.
RI− I C1 − Serial Data Input. Inverting Bus LVDS differential input.
PWRDN I D3 Powerdown. TTL level input. PWRDN driven low shuts down the PLL and
tri-states outputs putting the device into a low power sleep mode.
LOCK O E1 LOCK goes low when the Deserializer PLL locks onto the embedded clock
edge. CMOS level output. Totem pole output structure, does not directly
support wired OR connections.
RCLK O E2 Recovered Clock. Parallel data rate clock recovered from embedded clock.
Used to strobe ROUT, CMOS level output.
REN I D1 Output Enable. TTL level input. When driven low, tri-states ROUT0–ROUT9
and RCLK.
DVCC I A7, B7, C5, C6, Digital Circuit power supply.
D5
DGND I A1, A6, B5, D7, Digital Circuit ground.
E4, E7, G3
AVCC I B1, C2, F1, F2, Analog power supply (PLL and Analog Circuits).
G1
AGND I A4, B2, F3, F4, Analog ground (PLL and Analog Circuits).
G2
REFCLK I A3 Use this pin to supply a REFCLK signal for the internal PLL frequency.
TDI I F6 Test Data Input to support IEEE 1149.1. There is an internal pullup resistor
that defaults this input to high per IEEE 1149.1.
TDO O G6 Test Data Output to support IEEE 1149.1
TMS I G7 Test Mode Select Input to support IEEE 1149.1. There is an internal pullup
resistor that defaults this input to high per IEEE 1149.1.
TCK I E5 Test Clock Input to support IEEE 1149.1
TRST I E6 Test Reset Input to support IEEE 1149.1. There is an internal pullup resistor
that defaults this input to high per IEEE 1149.1.
N/C N/A A2, C3, D4, E3 Leave open circuit, do not connect
SPACER
Deserializer Truth Table
INPUTS OUTPUTS
PWRDN REN ROUT [0:9]
(1)
LOCK
(2)
RCLK
(3)(1)
H
(4)
H Z H Z
H H Active L Active
L X Z Z Z
H L Z Active Z
(1) ROUT and RCLK are tri-stated when LOCK is asserted High.
(2) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
(3) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined
by RCLK_R/F.
(4) During Power-up.
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