Datasheet
SCAN921025H, SCAN921226H
www.ti.com
SNLS185C –OCTOBER 2004–REVISED MAY 2013
Serializer Pin Descriptions
Pin Name I/O Ball Id. Description
DIN I A3, B1, C1, D1, Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit
D2, D3, E1, E2, input register.
F2, F4
TCLKR/F I G3 Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects
TCLK active edge for strobing of DIN data. High selects rising edge. Low
selects falling edge.
DO+ O D7 + Serial Data Output. Non-inverting Bus LVDS differential output.
DO− O D5 − Serial Data Output. Inverting Bus LVDS differential output.
DEN I D6 Serial Data Output Enable. LVTTL level input. A low puts the Bus LVDS
outputs in tri-state.
PWRDN I C7 Powerdown. LVTTL level input. PWRDN driven low shuts down the PLL
and tri-states outputs putting the device into a low power sleep mode.
TCLK I E4 Transmit Clock. LVTTL level input. Input for 20MHz – 80MHz system clock.
SYNC I A4, B3 Assertion of SYNC (high) for at least 1024 synchronization symbols to be
transmitted on the Bus LVDS serial output. Synchronization symbols
continue to be sent if SYNC continues to be asserted. TTL level input. The
two SYNC pins are ORed.
DVCC I C3, C4, E5 Digital Circuit power supply.
DGND I A1, C2, F5, E6, Digital Circuit ground.
G4
AVCC I A5, A6, B4, B7, Analog power supply (PLL and Analog Circuits).
G5
AGND I B5, B6, C6, E7, Analog ground (PLL and Analog Circuits).
F7
TDI I F1 Test Data Input to support IEEE 1149.1. There is an internal pullup resistor
that defaults this input to high per IEEE 1149.1.
TDO O G1 Test Data Output to support IEEE 1149.1
TMS I E3 Test Mode Select Input to support IEEE 1149.1. There is an internal pullup
resistor that defaults this input to high per IEEE 1149.1.
TCK I F3 Test Clock Input to support IEEE 1149.1
TRST I G2 Test Reset Input to support IEEE 1149.1. There is an internal pullup resistor
that defaults this input to high per IEEE 1149.1.
N/C N/A A2, A7, B2, C5, Leave open circuit, do not connect
D4, F6, G6, G7
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