Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers LVDS BGA 49

SCAN921025H, SCAN921226H

www.ti.com

SNLS185C –OCTOBER 2004–REVISED MAY 2013

SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes

with IEEE 1149.1 (JTAG) and at-speed BIST

Check for Samples: SCAN921025H, SCAN921226H

FEATURES

DESCRIPTION

The SCAN921025H transforms a 10-bit wide parallel

• High Temperature Operation to 125°C

LVCMOS/LVTTL data bus into a single high speed

• IEEE 1149.1 (JTAG) Compliant and At-Speed

Bus LVDS serial data stream with embedded clock.

BIST Test Mode

The SCAN921226H receives the Bus LVDS serial

• Clock Recovery from PLL Lock to Random

data stream and transforms it back into a 10-bit wide

parallel data bus and recovers parallel clock.

Data Patterns

• Ensured Transition Every Data Transfer Cycle

Both devices are compliant with IEEE 1149.1

Standard for Boundary Scan Test. IEEE 1149.1

• Chipset (Tx + Rx) Power Consumption < 600

features provide the design or test engineer access

mW (Typ) @ 80 MHz

via a standard Test Access Port (TAP) to the

• Single Differential Pair Eliminates Multi-

backplane or cable interconnects and the ability to

Channel Skew

verify differential signal integrity. The pair of devices

• 800 Mbps Serial Bus LVDS Data Rate (at 80

also features an at-speed BIST mode which allows

the interconnects between the Serializer and

MHz Clock)

Deserializer to be verified at-speed.

• 10-bit Parallel Interface for 1 Byte Data Plus 2

Control Bits

The SCAN921025H transmits data over backplanes

or cable. The single differential pair data path makes

• Synchronization Mode and LOCK Indicator

PCB design easier. In addition, the reduced cable,

• Programmable Edge Trigger on Clock

PCB trace count, and connector size tremendously

• High Impedance on Receiver Inputs When

reduce cost. Since one output transmits clock and

Power is Off

data bits serially, it eliminates clock-to-data and data-

to-data skew. The powerdown pin saves power by

• Bus LVDS Serial Output Rated for 27Ω Load

reducing supply current when not using either device.

• Small 49-Lead NFBGA Package

Upon power up of the Serializer, you can choose to

activate synchronization mode or allow the

APPLICATIONS

Deserializer to use the synchronization-to-random-

data feature. By using the synchronization mode, the

• Automotive

Deserializer will establish lock to a signal within

• Industrial

specified lock times. In addition, the embedded clock

• Military/Aerospace

ensures a transition on the bus every 12-bit cycle.

This eliminates transmission errors due to charged

cable conditions. Furthermore, you may put the

SCAN921025H output pins into tri-state to achieve a

high impedance state. The PLL can lock to

frequencies between 20 MHz and 80 MHz.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST Check for Samples: SCAN921025H, SCAN921226H FEATURES DESCRIPTION • • The SCAN921025H transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock.
PAGE 2
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com Block Diagram Figure 1.
PAGE 3
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Functional Description The SCAN921025H and SCAN921226H are a 10-bit Serializer and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from 20 to 80 MHz. The chipset is also capable of driving data over Unshielded Twisted Pair (UTP) cable.
PAGE 4
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0–ROUT9 is invalid. The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled by the RCLK_R/F input. See Figure 14.
PAGE 5
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Tri-state The Serializer enters tri-state when the DEN pin is driven low. This puts both driver output pins (DO+ and DO−) into tri-state. When you drive DEN high, the Serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When you drive the REN pin low, the Deserializer enters tri-state.
PAGE 6
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com DIN8 Held Low-DIN9 Held High Creates an RMT Pattern Figure 2. RMT Patterns Seen on the Bus LVDS Serial Output These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage −0.3V to (VCC +0.
PAGE 7
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN) VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA -0.86 −1.
PAGE 8
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ IILR Input Current VCC = 3.6V, VIN = 0V, pins TMS, TDI, and TRST -20 -10 VOH High Level Output Voltage VCC = 3.0V, IOH = −12 mA, TDO output 2.2 2.6 VOL Low Level Output Voltage VCC = 3.
PAGE 9
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tRFCP REFCLK Period 12.5 T 50.
PAGE 10
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com SCAN Circuitry Timing Requirements Min Typ fMAX Symbol Maximum TCK Clock Frequency 25.0 50.0 tS TDI to TCK, H or L 1.0 ns tH TDI to TCK, H or L 2.0 ns tS TMS to TCK, H or L 2.5 ns tH TMS to TCK, H or L 1.5 ns tW TCK Pulse Width, H or L 10.0 ns tW TRST Pulse Width, L 2.5 ns tREC Recovery Time, TRST to TCK 2.
PAGE 11
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 AC Timing Diagrams and Test Circuits Figure 3. “Worst Case” Serializer ICC Test Pattern Figure 4. “Worst Case” Deserializer ICC Test Pattern Figure 5. Serializer Bus LVDS Output Load and Transition Times Figure 6. Deserializer CMOS/TTL Output Load and Transition Times Figure 7.
PAGE 12
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com Timing shown for TCLK_R/F = LOW Figure 8. Serializer Setup/Hold Times Figure 9. Serializer Tri-state Test Circuit and Timing Figure 10.
PAGE 13
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Figure 11. SYNC Timing Delays Figure 12. Serializer Delay Figure 13.
PAGE 14
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com Timing shown for RCLK_R/F = LOW Duty Cycle (tRDC) = Figure 14. Deserializer Data Valid Out Times Figure 15.
PAGE 15
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Figure 16. Deserializer PLL Lock Times and PWRDN Tri-state Delays Figure 17.
PAGE 16
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. Figure 18.
PAGE 17
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 APPLICATION INFORMATION USING THE SCAN921025H AND SCAN921226H The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of parallel LVTTL data over a serial Bus LVDS link up to 800 Mbps. An on-board PLL serializes the input data and embeds two clock bits within the data stream.
PAGE 18
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com HOT INSERTION All the BLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 22.
PAGE 19
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Figure 20. Deterministic Jitter and Ideal Bit Position tRNMI-L is the ideal noise margin on the left of the figure, it is a negative value to indicate early with respect to ideal. tRNMI-R is the ideal noise margin on the right of the above figure, it is a positive value to indicate late with respect to ideal. Figure 21. Ideal Deserializer Noise Margin (tRNMI) and Sampling Window Figure 22.
PAGE 20
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com Pin Diagrams Figure 23. SCAN921025HSM - Serializer (Top View) Figure 24. Figure 25.
PAGE 21
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 Serializer Pin Descriptions Pin Name I/O Ball Id. Description DIN I TCLKR/F I G3 Transmit Clock Rising/Falling strobe select. LVTTL level input. Selects TCLK active edge for strobing of DIN data. High selects rising edge. Low selects falling edge. DO+ O D7 + Serial Data Output. Non-inverting Bus LVDS differential output. DO− O D5 − Serial Data Output. Inverting Bus LVDS differential output.
PAGE 22
SCAN921025H, SCAN921226H SNLS185C – OCTOBER 2004 – REVISED MAY 2013 www.ti.com Deserializer Pin Descriptions Pin Name I/O Ball Id. ROUT O A5, B4, B6, C4, C7, D6, F5, F7, G4, G5 RCLKR/F I B3 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. RI+ I D2 + Serial Data Input. Non-inverting Bus LVDS differential input. RI− I C1 − Serial Data Input.
PAGE 23
SCAN921025H, SCAN921226H www.ti.com SNLS185C – OCTOBER 2004 – REVISED MAY 2013 REVISION HISTORY Changes from Revision B (May 2013) to Revision C • Page Changed layout of National Data Sheet to TI format. .........................................................................................................
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 1-Dec-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SCAN921025HSMX/NOP B NFBGA NZA 49 2000 330.0 16.4 7.3 7.3 2.1 12.0 16.0 Q1 SCAN921226HSMX/NOP B NFBGA NZA 49 2000 330.0 16.4 7.3 7.3 2.1 12.0 16.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SCAN921025HSMX/NOPB NFBGA NZA 49 2000 367.0 367.0 38.0 SCAN921226HSMX/NOPB NFBGA NZA 49 2000 367.0 367.0 38.
PAGE 28
MECHANICAL DATA NZA0049A SLC49A (Rev B) www.ti.
PAGE 29
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.