Datasheet
HCLK
DMMCLK
DMMSYNC
DMMDATA
DMMENA
D00 D01 D10 D11 D20 D21
D30
D31 D40 D41 D50
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011
www.ti.com
7.17.3 DMMENA Timing
Figure 7-26. DMMENA Timing
The above figure shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode,
data width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to
filling up of the internal buffers. The DMMENA signal is shown asserted, after the first two packets have
been received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets
D4, D5, D6, D7. Packet D8 would result in an overflow. Once DMMENA is asserted, the DMM expects to
stop receiving packets after 4 HCLK cycles; once DMMENA is de-asserted, the DMM can handle packets
immediately (after 0 HCLK cycles).
7.18 MibADC
7.18.1 MibADC
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are
given with respect to ADREFLO unless otherwise noted.
Table 7-27. MibADC
Resolution 12 bits (4096 values)
Monotonic Assured
Output conversion φcode 00h to FFFh [00 for V
AI
≤AD
REFLO
; FFF for V
AI
≥ AD
REFHI
]
7.18.2 MibADC Recommended Operating Conditions
Table 7-28. MibADC Recommended Operating Conditions
(1)
MIN MAX UNIT
AD
REFHI
A-to-D high-voltage reference source 3 3.6 V
AD
REFLO
A-to-D low-voltage reference source 0 0.3 V
V
AI
Analog input voltage AD
REFLO
AD
REFHI
V
I
AIC
Analog input clamp current
(2)
-2 2 mA
(V
AI
< V
SSAD
– 0.3 or V
AI
> V
CCAD
+
0.3)
(1) For V
CCAD
and V
SSAD
recommended operating conditions, see the "device recommended operating conditions" table.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
94 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated
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