Datasheet

t(DMM)
cyc
t
r
t
f
t(DMM)
h
t(DMM)
l
t(DMM)
dsu
t(DMM)
dho
DMMSYNC
DMMCLK
DMMDATA
t(DMM)
sho
t(DMM)
ssu
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
7.17 DMM Timings
7.17.1 DMMCLK Timing
Figure 7-24. DMMCLK Timing
Table 7-25. DMMCLK Timing
Parameter Minimum Description
t(DMM)
cyc
t
c(HCLK)
* 2 Clock period
t(DMM)
h
t(DMM)
cyc
/2-(t
r
+t
f
)/2 High pulse width
t(DMM)
l
t(DMM)
cyc
/2-(t
r
+t
f
)/2 Low pulse width
7.17.2 DMMDATA Timing
Figure 7-25. DMMDATA Timing
Table 7-26. DMMDATA Timing
Parameter Minimum Description
t(DMM)
ssu
2ns SYNC active to clk falling edge setup time
t(DMM)
sho
3ns clk falling edge to SYNC deactive hold time
t(DMM)
dsu
2ns DATA to clk falling edge setup time
t(DMM)
dho
3ns clk falling edge to DATA hold time
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