Datasheet

t(RTP)
cyc
t
r
t
f
t(RTP)
h
t(RTP)
l
t(RTP)
dsu
t(RTP)
dho
RTPSYNC
RTPCLK
RTPDATA
t(RTP)
sho
t(RTP)
ssu
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
7.16 RTP Timings
7.16.1 RTPCLK Timing
Figure 7-21. RTPCLK Timing
Table 7-22. RTPCLK Timing
Parameter Minimum Description
t(RTP)
cyc
10 ns Clock period (depending on HCLK divide
ratio)
t(RTP)
h
(t(RTP)
cyc
/2) - ((t
r
+t
f
)/2) -1.5 High pulse width (depending on HCLK divide
ratio and load on pin)
t(RTP)
l
(t(RTP)
cyc
/2) - ((t
r
+t
f
)/2) -1.5 Low pulse width (depending on HCLK divide
ratio and load on pin)
7.16.2 RTPDATA Timing
Figure 7-22. RTPDATA Timing
Table 7-23. RTPDATA Timing
Parameter Minimum Description
t(RTP)
dsu
0.5 t(RTP)
cyc
-3ns Data setup time
t(RTP)
dho
0.5 t(RTP)
cyc
-2ns Data hold time
t(RTP)
ssu
0.5 t(RTP)
cyc
-3ns SYNC setup time
t(RTP)
sho
0.5 t(RTP)
cyc
-2ns SYNC hold time
Note: The timings in this table are measured with a 50pF and 50µA load. And they are measured at the 50% point, not 20% or 80% point.
Copyright © 2010–2011, Texas Instruments Incorporated Peripheral and Electrical Specifications 91
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