Datasheet

EMIFCS[3:0]
EMIFBADD[1:0]
EMIFADD[21:0]
EMIFWE
EMIFD[15:0]
EMIFOE
12
1
13
15
17
19
18
16
14
2120
t(ETM)
cyc
t(ETM)
r
t(ETM)
f
t(ETM)
h
t(ETM)
l
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
7.14.2 Write Timing (Asynchronous RAM)
Figure 7-18. Asynchronous Memory Write Timing for EMIF
7.15 ETM Timings
7.15.1 ETMTRACECLK Timing
Figure 7-19. ETMTRACECLK Timing
Table 7-20. ETMTRACECLK Timing
Parameter Minimum Maximum Description
f(ETM)
cyc
40MHz Clock frequency
t(ETM)
cyc
25ns Clock period
t(ETM)
l
2ns Low pulse width
t(ETM)
h
2ns High pulse width
t(ETM)
r
3ns Clock and data rise time
t(ETM)
f
3ns Clock and data fall time
Copyright © 2010–2011, Texas Instruments Incorporated Peripheral and Electrical Specifications 89
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