Datasheet

TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011 www.ti.com
7.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input,
SPISIMO = input, and SPISOMI = output)
Table 7-16. SPI Slave Mode External Timing Parameters
(1)(2)(3)
NO. MIN MAX Unit
1 t
c(SPC)S
Cycle time, SPICLK
(4)
90 ns
2
(5)
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0) 30 ns
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1) 30
3
(5)
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0) 30 ns
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1) 30
4
(5)
t
d(SOMI-
Delay time, SPISOMI data valid after SPICLK low t
rf(SOMI)
+15 ns
SPCL)S
(clock polarity = 0)
t
d(SOMI-
Delay time, SPISOMI data valid after SPICLK high t
rf(SOMI)
+15
SPCH)S
(clock polarity = 1)
5
(5)
t
V(SPCL-
Valid time, SPISOMI data valid after SPICLK high 0 ns
SOMI)S
(clock polarity =0)
t
V(SPCH-
Valid time, SPISOMI data valid after SPICLK low 0
SOMI)S
(clock polarity =1)
6
(5)
t
su(SIMO-
Setup time, SPISIMO before SPICLK high (clock 4 ns
SPCH)S
polarity = 0)
t
su(SIMO-
Setup time, SPISIMO before SPICLK low (clock 4
SPCL)S
polarity = 1)
7
(5)
t
h(SPCH-
Hold time, SPISIMO data valid after SPICLK high 6 ns
SIMO)S
(clock polarity = 0)
t
h(SPCL-
Hold time, SPISIMO data valid after SPICLK low 6
SIMO)S
(clock polarity = 1)
8 t
d(SPCH-
Delay time, SPIENAn high after last SPICLK high 1.5t
c(VCLK)
2.5t
c(VCLK)
+t
r(ENAn)
+ 26 ns
SENAH)S
(clock polarity = 0)
t
d(SPCL-
Delay time, SPIENAn high after last SPICLK low 1.5t
c(VCLK)
2.5t
c(VCLK)
+t
r(ENAn)
+ 26
SENAH)S
(clock polarity = 1)
9 t
d(SCSL-
Delay time, SPIENAn low after SPICSn low (if new t
f(ENAn)
t
c(VCLK)
+ t
f(ENAn)
+ 18 ns
SENAL)S
data has been written to the SPI buffer)
10 t
d(SCSL-
Delay time, SOMI valid after SPICSn low (if new data t
c(VCLK)
2t
c(VCLK)
+ t
rf(SOMI)
+ 20 ns
SOMI)S
has been written to the SPI buffer)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) t
c(VCLK)
= interface clock cycle time = 1 /f
(VCLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in Slave mode, the following must be true:
t
c(SPC)S
> 2t
c(VCLK)
and t
c(SPC)S
>= 90 ns.
t
w(SPCH)S
> t
c(VCLK)
and t
w(SPCL)S
> t
c(VCLK)
.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
84 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated
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