Datasheet

Master In Data
Must Be Valid
Master Out Data Is Valid
Data Valid
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
2
1
3
6
7
5
4
SPICLK
(clock polarity = 0)
SPISIMO
SPICS
Master Out Data Is Valid
SPICLK
(clock polarity = 1)
SPIENA
10
Write to buffer
11
8
9
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
Figure 7-11. SPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 7-12. SPI Master Mode Chip Select timing (CLOCK PHASE = 1)
Copyright © 2010–2011, Texas Instruments Incorporated Peripheral and Electrical Specifications 81
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