Datasheet

SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
7
Master In Data
Must Be Valid
Master Out Data Is Valid
2
1
3
5
4
6
SPICLK
(clock polarity = 0)
SPISIMO
SPICSn
Master Out Data Is Valid
SPICLK
(clock polarity = 1)
SPIENAn
10
Write to buffer
11
8
9
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com SPNS141F–AUGUST 2010– REVISED JULY 2011
Figure 7-9. SPI Master Mode External Timing (CLOCK PHASE = 0)
Figure 7-10. SPI Master Mode Chip Select timing (CLOCK PHASE = 0)
Copyright © 2010–2011, Texas Instruments Incorporated Peripheral and Electrical Specifications 79
Submit Documentation Feedback
focus.ti.com: TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106