Datasheet
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141F–AUGUST 2010– REVISED JULY 2011
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7.9 SPI Master Mode Timing Parameters
7.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)
Table 7-13. SPI Master Mode External Timing Parameters
(1)(2)(3)
NO. MIN MAX Unit
1 t
c(SPC)M
Cycle time, SPICLK
(4)
50 256t
c(VCLK)
ns
2
(5)
t
w(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0) 0.5t
c(SPC)M
– 3 – t
r
0.5t
c(SPC)M
+ 5 ns
t
w(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1) 0.5t
c(SPC)M
– 3 – t
f
0.5t
c(SPC)M
+ 5
3
(5)
t
w(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0) 0.5t
c(SPC)M
– 3 – t
f
0.5t
c(SPC)M
+ 5 ns
t
w(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1) 0.5t
c(SPC)M
– 3 – t
r
0.5t
c(SPC)M
+ 5
4
(5)
t
d(SIMO-SPCL)M
Delay time, SPISIMO valid before SPICLK low 0.5t
c(SPC)M
– 10 ns
(clock polarity = 0)
t
d(SIMO-SPCH)M
Delay time, SPISIMO valid before SPICLK high 0.5t
c(SPC)M
– 10
(clock polarity = 1)
5
(5)
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low 0.5t
c(SPC)M
– t
f(SPC)
-7 ns
(clock polarity = 0)
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high 0.5t
c(SPC)M
– t
r(SPC)
-7
(clock polarity = 1)
6
(5)
t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low (clock t
f(SPC)
ns
polarity = 0)
t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high (clock t
r(SPC)
+ 4
polarity = 1)
7
(5)
t
h(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK low 10 ns
(clock polarity = 0)
t
h(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK high 10
(clock polarity = 1)
8
(6)
t
C2TDELAY
Setup time CS active until SPICLK high, assumes (C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+ ns
that SPInENA is low at t
SPIENA
(clock polarity = 0) 2)*t
c(VCLK)
- t
f(SPICS)
+ 2)*t
c(VCLK)
- t
f(SPICS)
+
t
r(SPC)
- 9 t
r(SPC)
+ 5
Setup time CS active until SPICLK low, assumes (C2TDELAY+CSHOLD+ (C2TDELAY+CSHOLD+ ns
that SPInENA is low at t
SPIENA
(clock polarity = 1) 2)*t
c(VCLK)
- t
f(SPICS)
+ 2)*t
c(VCLK)
- t
f(SPICS)
+
t
f(SPC)
- 9 t
f(SPC)
+ 5
9
(6)
t
T2CDELAY
Hold time SPICLK low until CS inactive (clock 0.5*t
c(SPC)M
+ 0.5*t
c(SPC)M
+ ns
polarity = 0) T2CDELAY*t
c(VCLK)
+ T2CDELAY*t
c(VCLK)
+
t
c(VCLK)
- t
c(VCLK)
-
t
f(SPC)
+ t
r(SPICS)
- 5 t
f(SPC)
+ t
r(SPICS)
+ 10
Hold time SPICLK high until CS inactive (clock 0.5*t
c(SPC)M
+ 0.5*t
c(SPC)M
+ ns
polarity = 1) T2CDELAY*t
c(VCLK)
+ T2CDELAY*t
c(VCLK)
+
t
c(VCLK)
- t
c(VCLK)
-
t
r(SPC)
+ t
r(SPICS)
- 5 t
r(SPC)
+ t
r(SPICS)
+ 10
10 t
SPIENA
SPIENAn Sample point C2TDELAY * t
c(VCLK)
- C2TDELAY * t
c(VCLK)
ns
t
f(SPICS)
- 20
11 t
SPIENAW
SPIENAn Sample point from write to buffer (C2TDELAY+2)*t
c(VCLK)
ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) t
c(VCLK)
= interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t
c(SPC)M
≥ (PS +1)t
c(VCLK)
≥ 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t
c(SPC)M
= 2t
c(VCLK)
≥ 50 ns. The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY are programmed in the SPIDELAY register
78 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated
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